Improve Yield and Quality Through Testability Analysis of VLSI Circuits. - David M. Wu; Charles E. Radke; C. C. Beh (ITC, 1984)

Statistical AC Test Coverage. - David M. Wu; Charles E. Radke; J. Paul Roth (ITC, 1986)

Delay Test Effectiveness Evaluation of LSSD-Based VLSI Vogic Circuits. - David M. Wu; Charles E. Radke (DAC, 1991)

Statistical sensitivity simulation for integrating design and testing of MOSFET integrated circuits. - Waisum Wong; Juin J. Liou; Jiann-Shiun Yuan; David M. Wu (VTS, 1991)

An optimized delay testing technique for LSSD-based VLSI logic circuits. - David M. Wu (VTS, 1991)

Testing the impact of process defects on ECL power-delay performance. - Jiann-Shiun Yuan; Juin J. Liou; David M. Wu (VTS, 1991)

Multiple redundancy removal during test generation and synthesis. - David M. Wu; Robert M. Swanson (VTS, 1992)

DFT is all I can afford, who cares about Design for Yield or Design for Reliability! - David M. Wu (ITC, 1999)

"DFY and DFR are more important than DFT". - David M. Wu (ITC, 1999)

Cold Delay Defect Screening. - Chao-Wen Tseng; Edward J. McCluskey; Xiaoping Shao; David M. Wu (VTS, 2000)

Trouble With Scan. - David M. Wu (ITC, 2002)

H-DFT: A Hybrid DFT Architecture For Low-Cost High Quality Structural Testing. - David M. Wu; Mike Lin; Subhasish Mitra; Kee Sup Kim; Anil Sabbavarapu; Talal Jaber; Pete Johnson; Dale March; Greg Parrish (ITC, 2003)

An Optimized DFT and Test Pattern Generation Strategy for an Intel High Performance Microprocessor. - David M. Wu; Mike Lin; Madhukar Reddy; Talal Jaber; Anil Sabbavarapu; Larry Thatcher (ITC, 2004)

A Low Cost, High Quality Embedded Array DFT Technique for High Performance Processors. - Zhuoyu Bao; Suriya A. Kumar; David M. Wu; Vimal K. Natarajan; Mike Lin (DELTA, 2006)