A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET. - James Hudner; Declan Carey; Ronan Casey; Kay Hearne; Pedro Wilson de Abreu Farias Neto; Ilias Chlis; Marc Erett; Chi Fung Poon; Asma Laraba; Hongtao Zhang 002; Sai Lalith Chaitanya Ambatipudi; David Mahashin; et al. (VLSI Circuits, 2018)

A 0.5-28GB/S Wireline Tranceiver with 15-Tap DFE and Fast-Locking Digital CDR in 7NM FinFET. - Jay Im; Stanley Chen; Dave Freitas; Adam Chou; Lei Zhou; Ian Zhuang; Tim Cronin; David Mahashin; Winson Lin; Kok Lim Chan; Hongyuan Zhao; Kee Hian Tan; et al. (VLSI Circuits, 2018)

A 50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET. - Mayank Raj; Yohan Frans; Sai Lalith Chaitanya Ambatipudi; David Mahashin; Peter De Heyn; Sadhishkumar Balakrishnan; Joris Van Campenhout; Jimmy Grayson; Marc Epitaux; Ken Chang (VLSI Circuits, 2019)

50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET. - Mayank Raj; Yohan Frans; Ping-Chuan Chiang; Sai Lalith Chaitanya Ambatipudi; David Mahashin; Peter De Heyn; Sadhishkumar Balakrishnan; Joris Van Campenhout; Jimmy Grayson; Marc Epitaux; Ken Chang (ECOC, 2020)

6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET. - Jay Im; Kevin Zheng; Adam Chou; Lei Zhou; Jae Wook Kim; Stanley Chen; Yipeng Wang 003; Hao-Wei Hung; Kee Hian Tan; Winson Lin; Arianne Roldan; Declan Carey; et al. (ISSCC, 2020)

Design of a 50-Gb/s Hybrid Integrated Si-Photonic Optical Link in 16-nm FinFET. - Mayank Raj; Yohan Frans; Ping-Chuan Chiang; Sai Lalith Chaitanya Ambatipudi; David Mahashin; Peter De Heyn; Sadhishkumar Balakrishnan; Joris Van Campenhout; Jimmy Grayson; Marc Epitaux; Ken Chang (IEEE J. Solid State Circuits, 2020)

A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET. - Jay Im; Kevin Zheng; Chuen-Huei Adam Chou; Lei Zhou; Jae Wook Kim; Stanley Chen; Yipeng Wang 003; Hao-Wei Hung; Kee Hian Tan; Winson Lin; Arianne Roldan; Declan Carey; et al. (IEEE J. Solid State Circuits, 2021)

A O.96pJ/b 7 × 50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies. - Mayank Raj; Chuan Xie; Ade Bekele; Adam Chou; Wenfeng Zhang; Ying Cao 010; Jae Wook Kim; Nakul Narang; Hongyuan Zhao; Yipeng Wang 003; Kee Hian Tan; Winson Lin; et al. (ISSCC, 2023)