A Reliable Reconfiguration Controller for Fault-Tolerant Embedded Systems on Multi-FPGA Platforms. - Cristiana Bolchini; Luca Fossati; David Merodio Codinachs; Antonio Miele; Chiara Sandionigi (DFT, 2010)

A reliable fault classifier for dependable systems on SRAM-based FPGAs. - Cristiana Bolchini; Chiara Sandionigi; Luca Fossati; David Merodio Codinachs (IOLTS, 2011)

Preface. - Khaled Benkrid; Didier Keymeulen; David Merodio; Michael Newell; Rainer Wansch; Umeshkumar D. Patel; Ahmet T. Erdogan; Niels Hadaschik; Luca Sterpone; Jelle Poupaert; Massimo Violante (AHS, 2013)

A fully-automated flow for ITAR-free rad-hard Atmel FPGAs. - Nikos Andrikos; Massimo Violante; David Merodio Codinachs (IOLTS, 2013)

Guest Editors' introduction: Special section on adaptive hardware and systems. - Khaled Benkrid; Didier Keymeulen; Umeshkumar D. Patel; David Merodio Codinachs (IEEE Trans. Computers, 2013)

Validation of a tool for estimating the effects of soft-errors on modern SRAM-based FPGAs. - Marco Desogus; Luca Sterpone; David Merodio Codinachs (IOLTS, 2014)

In-flight reconfigurable FPGA-based space systems. - Norma Montealegre; David Merodio; Agustín Fernández; Philippe Armbruster (AHS, 2015)

On the design of highly reliable system-on-chip using dynamically reconfigurable FPGAs. - Boyang Du; Luca Sterpone; Lorenzo Venditti; David Merodio Codinachs (ReCoSoC, 2015)

A new EDA flow for the mitigation of SEUs in dynamic reconfigurable FPGAs. - Boyang Du; Luca Sterpone; David Merodio Codinachs (ETS, 2016)

Analysis of radiation-induced SEUs on dynamic reconfigurable systems. - Luca Sterpone; Luca Boragno; David Merodio Codinachs (ReCoSoC, 2016)

Effective Mitigation of Radiation-induced Single Event Transient on Flash-based FPGAs. - Luca Sterpone; Sarah Azimi; Boyang Du; David Merodio Codinachs; Raoul Grimoldi (ACM Great Lakes Symposium on VLSI, 2017)

BRAVE NG-MEDIUM FPGA reconfiguration through SpaceWire: example use case and performance analysis. - Klemen Bravhar; Victor Martins; Lucana Santos; David Merodio Codinachs (AHS, 2018)

Evaluation Methodology and Reconfiguration Tests on the New European NG-MEDIUM FPGA. - Konstantinos Maragos 001; Vasileios Leon; George Lentaris; Dimitrios Soudris; David González Arjona; Ruben Domingo; Antonio Pastor 001; David Merodio Codinachs; Isabelle Conway (AHS, 2018)

A Novel Error Rate Estimation Approach forUltraScale+ SRAM-based FPGAs. - Luca Sterpone; Sarah Azimi; Ludovica Bozzoli; Boyang Du; Thomas Lange; Maximilien Glorieux; Dan Alexandrescu; Cesar Boatella Polo; David Merodio Codinachs (AHS, 2018)

SETA: A CAD Tool for Single Event Transient Analysis and Mitigation on Flash-Based FPGAs. - Sarah Azimi; Boyang Du; Luca Sterpone; David Merodio Codinachs; L. Cattaneo (SMACD, 2018)

A new CAD tool for Single Event Transient Analysis and mitigation on Flash-based FPGAs. - Sarah Azimi; Boyang Du; Luca Sterpone; David Merodio Codinachs; Raoul Grimoldi; L. Cattaneo (Integr., 2019)

Development and Testing on the European Space-Grade BRAVE FPGAs: Evaluation of NG-Large Using High-Performance DSP Benchmarks. - Vasileios Leon; Ioannis Stamoulias; George Lentaris; Dimitrios Soudris; David González Arjona; Ruben Domingo; David Merodio Codinachs; Isabelle Conway (IEEE Access, 2021)

Analysis of Proton-induced Single Event Effect in the On-Chip Memory of Embedded Process. - Corrado De Sio; Sarah Azimi; Luca Sterpone; David Merodio Codinachs (DFT, 2022)

Radiation-induced Effects on DMA Data Transfer in Reconfigurable Devices. - Andrea Portaluri; Sarah Azimi; Corrado De Sio; Luca Sterpone; David Merodio Codinachs (IOLTS, 2022)

EuFRATE: European FPGA Radiation-hardened Architecture for Telecommunications. - Ludovica Bozzoli; Antonino Catanese; Emilio Fazzoletto; Eugenio Scarpa; Diana Goehringer; Sergio A. Pertuz 001; Lester Kalms; Cornelia Wulf; Najdet Charaf; Luca Sterpone; Sarah Azimi; Daniele Rizzieri; et al. (DATE, 2023)

PyXEL: Exploring Bitstream Analysis to Assess and Enhance the Robustness of Designs on FPGAs. - Corrado De Sio; Sarah Azimi; Luca Sterpone; David Merodio Codinachs; Filomena Decuzzi (SMACD, 2023)

Payload-XL: A Platform for the In-Orbit Validation of the BRAVE FPGA. - Felipe Viel; Kleber R. Gouveia; Edilberto Costa; Márcio Oliveira; Miguel Boing; André Martins Pio de Mattos; Gabriel Mariano Marcelino; David Merodio Codinachs; Laio Oriel Seman; Eduardo Augusto Bezerra (IEEE Embed. Syst. Lett., 2023)

Development of High-Performance DSP Algorithms on the European Rad-Hard NG-ULTRA SoC FPGA. - Vasileios Leon; Anastasios Xynos; Dimitrios Soudris; George Lentaris; Ruben Domingo; Arturo Perez; David González Arjona; Isabelle Conway; David Merodio Codinachs (CoRR, 2024)