Resilient random modulo cache memories for probabilistically-analyzable real-time systems. - David Trilla; Carles Hernández 001; Jaume Abella 001; Francisco J. Cazorla (IOLTS, 2016)

Improving Early Design Stage Timing Modeling in Multicore Based Real-Time Systems. - David Trilla; Javier Jalle; Mikel Fernández; Jaume Abella 001; Francisco J. Cazorla (RTAS, 2016)

Modelling bus contention during system early design stages. - David Trilla; Carles Hernández 001; Jaume Abella 001; Francisco J. Cazorla (SIES, 2017)

Cache side-channel attacks and time-predictability in high-performance critical real-time systems. - David Trilla; Carles Hernández 001; Jaume Abella 001; Francisco J. Cazorla (DAC, 2018)

An Approach for Detecting Power Peaks During Testing and Breaking Systematic Pathological Behavior. - David Trilla; Carles Hernández 001; Jaume Abella 001; Francisco J. Cazorla (DSD, 2019)

Modeling the Impact of Process Variations in Worst-Case Energy Consumption Estimation. - David Trilla; Carles Hernández 001; Jaume Abella 001; Francisco J. Cazorla (DSD, 2019)

Randomization for Safer, more Reliable and Secure, High-Performance Automotive Processors. - David Trilla; Francisco J. Cazorla; Carles Hernández 001; Jaume Abella 001 (IEEE Des. Test, 2019)

Non-functional considerations of time-randomized processor architectures. - David Trilla (2020)

SafeSU: an Extended Statistics Unit for Multicore Timing Interference. - Guillem Cabo; Francisco Bas; Ruben Lorenzo; David Trilla; Sergi Alcaide; Miquel Moretó; Carles Hernández 001; Jaume Abella 001 (ETS, 2021)

SafeDE: a flexible Diversity Enforcement hardware module for light-lockstepping. - Francisco Bas; Sergi Alcaide; Ruben Lorenzo; Guillem Cabo; Guillermo Gil; Oriol Sala; Fabio Mazzocchetti; David Trilla; Jaume Abella 001 (IOLTS, 2021)

SafeTI: a Hardware Traffic Injector for MPSoC Functional and Timing Validation. - Oriol Sala; Sergi Alcaide; Guillem Cabo; Francisco Bas; Ruben Lorenzo; Pedro Benedicte; David Trilla; Guillermo Gil; Fabio Mazzocchetti; Jaume Abella 001 (IOLTS, 2021)

NOVIA: A Framework for Discovering Non-Conventional Inline Accelerators. - David Trilla; John-David Wellman; Alper Buyuktosunoglu; Pradip Bose (MICRO, 2021)

Worst-Case Energy Consumption: A New Challenge for Battery-Powered Critical Devices. - David Trilla; Carles Hernández 001; Jaume Abella 001; Francisco J. Cazorla (IEEE Trans. Sustain. Comput., 2021)

Enterprise-Class Cache Compression Design. - Alper Buyuktosunoglu; David Trilla; Bülent Abali; Deanna Postles Dunn Berger; Craig R. Walters; Jang-Soo Lee (HPCA, 2024)

14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration. - Maico Cassel dos Santos; Tianyu Jia; Joseph Zuckerman; Martin Cochet; Davide Giri; Erik Jens Loscalzo; Karthik Swaminathan; Thierry Tambe; Jeff Jun Zhang; Alper Buyuktosunoglu; Kuan-Lin Chiu; Giuseppe Di Guglielmo; et al. (ISSCC, 2024)