Interactive Outlining: An Improved Approach Using Active Contours. - Dirk Daneels; David Van Campenhout; Wayne Niblack; William Equitz; Ron Barber; Erwin Bellon; Freddy Fierens (Storage and Retrieval for Image and Video Databases (SPIE), 1993)

Timing verification of sequential domino circuits. - David Van Campenhout; Trevor N. Mudge; Karem A. Sakallah (ICCAD, 1996)

High-level design verification of microprocessors via error modeling. - David Van Campenhout; Hussain Al-Asaad; John P. Hayes; Trevor N. Mudge; Richard B. Brown (ACM Trans. Design Autom. Electr. Syst., 1998)

Specification and verification of pipelining in the ARM2 RISC microprocessor. - James K. Huggins; David Van Campenhout (ACM Trans. Design Autom. Electr. Syst., 1998)

High-Level Test Generation for Design Verification of Pipelined Microprocessors. - David Van Campenhout; Trevor N. Mudge; John P. Hayes (DAC, 1999)

Timing verification of sequential dynamic circuits. - David Van Campenhout; Trevor N. Mudge; Karem A. Sakallah (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Functional design verification for microprocessors by error modeling. - David Van Campenhout (1999)

Collection and Analysis of Microprocessor Design Errors. - David Van Campenhout; Trevor N. Mudge; John P. Hayes (IEEE Des. Test Comput., 2000)

Reasoning with Temporal Logic on Truncated Paths. - Cindy Eisner; Dana Fisman; John Havlicek; Yoad Lustig; Anthony McIsaac; David Van Campenhout (CAV, 2003)

The Definition of a Temporal Clock Operator. - Cindy Eisner; Dana Fisman; John Havlicek; Anthony McIsaac; David Van Campenhout (ICALP, 2003)