An integrated multiplier for complex numbers. - Vojin G. Oklobdzija; David Villeger; Thierry Soulas (J. VLSI Signal Process., 1994)

Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology. - Vojin G. Oklobdzija; David Villeger (IEEE Trans. Very Large Scale Integr. Syst., 1995)

A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach. - Vojin G. Oklobdzija; David Villeger; Simon S. Liu (IEEE Trans. Computers, 1996)