IBM Enterprise Systems multimode fiber optic technology. - Nancy R. Aulet; David W. Boerstler; George DeMario; Frank D. Ferraiolo; Curtis E. Hayward; Charles D. Heath; Allen L. Huffman; William R. Kelly; Gerald W. Peterson; Daniel J. Stigliani Jr. (IBM J. Res. Dev., 1992)

Design methodology for a 1.0 GHz microprocessor. - Stephen D. Posluszny; Naoaki Aoki; David Boerstler; Jeffrey L. Burns; Sang H. Dhong; Uttam Ghoshal; H. Peter Hofstee; David P. LaPotin; Kyung T. Lee; David Meltzer; Hung C. Ngo; Kevin J. Nowka; et al. (ICCD, 1998)

A 1.0-GHz single-issue 64-bit powerPC integer processor. - Joel Silberman; Naoaki Aoki; David Boerstler; Jeffrey L. Burns; Sang H. Dhong; Axel Essbaum; Uttam Ghoshal; David F. Heidel; H. Peter Hofstee; Kyung T. Lee; David Meltzer; Hung C. Ngo; et al. (IEEE J. Solid State Circuits, 1998)

A low-jitter PLL clock generator for microprocessors with lock range of 340-612 MHz. - David W. Boerstler (IEEE J. Solid State Circuits, 1999)

"Timing closure by design, " a high frequency microprocessor design methodology. - Stephen D. Posluszny; Naoaki Aoki; David Boerstler; Paula K. Coulman; Sang H. Dhong; Brian K. Flachs; H. Peter Hofstee; Nobuo Kojima; Ohsang Kwon; Kyung T. Lee; David Meltzer; Kevin J. Nowka; et al. (DAC, 2000)

A clock distribution network for microprocessors. - Phillip J. Restle; Timothy G. McNamara; David A. Webber; Peter J. Camporese; Kwok F. Eng; Keith A. Jenkins; David H. Allen; Michael J. Rohn; Michael P. Quaranta; David W. Boerstler; Charles J. Alpert; Craig A. Carter; et al. (IEEE J. Solid State Circuits, 2001)

A new test and characterization scheme for 10+ GHz low jitter wide band PLL. - Kazuhiko Miki; David Boerstler; Eskinder Hailu; Jieming Qi; Sarah Pettengill; Yuichi Goto (ASP-DAC, 2006)

A Circuit for Reducing Large Transient Current Effects on Processor Power Grids. - Eskinder Hailu; David W. Boerstler; Kazuhiko Miki; Jieming Qi; Michael Wang 001; Mack W. Riley (ISSCC, 2006)

Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor. - Dac C. Pham; Tony Aipperspach; David Boerstler; Mark Bolliger; Rajat Chaudhry; Dennis Cox; Paul E. Harvey; H. Peter Hofstee; Charles R. Johns; Jim Kahle; Atsushi Kameyama; John M. Keaty; et al. (IEEE J. Solid State Circuits, 2006)

Implementation of the 65nm Cell Broadband Engine. - Mack W. Riley; Brian K. Flachs; Sang H. Dhong; Gilles Gervais; Steve Weitzel; Michael Wang 001; David Boerstler; Mark Bolliger; John M. Keaty; Jürgen Pille; R. Berry; Osamu Takahashi; et al. (CICC, 2007)

A 1V 18GHz Clock Generator in a 65nm PD-SOI Technology. - Fadi H. Gebara; Jeremy D. Schaub; Tuyet Nguyen; Jarom Peña; Ivan Vo; David Boerstler; Kevin J. Nowka (ISSCC, 2007)

On-chip circuit for measuring multi-GHz clock signal waveforms. - Keith A. Jenkins; Phillip J. Restle; P. Z. Wang; D. Hogenmiller; David W. Boerstler; Thomas J. Bucelot (VTS, 2013)

True hardware random number generation implemented in the 32-nm SOI POWER7+ processor. - John S. Liberty; Adrian Barrera; David W. Boerstler; Thomas B. Chadwick; Scott R. Cottier; H. Peter Hofstee; Julie A. Rosser; Marty L. Tsai (IBM J. Res. Dev., 2013)

5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8TM microprocessor. - Zeynep Toprak Deniz; Michael A. Sperling; John F. Bulzacchelli; Gregory S. Still; Ryan Kruse; Seongwon Kim; David Boerstler; Tilman Gloekler; Raphael Robertazzi; Kevin Stawiasz; Tim Diemoz; George English; et al. (ISSCC, 2014)

The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking. - Eric J. Fluhr; Steve Baumgartner; David W. Boerstler; John F. Bulzacchelli; Timothy Diemoz; Daniel Dreps; George English; Joshua Friedrich; Anne Gattiker; Tilman Gloekler; Christopher J. Gonzalez; Jason Hibbeler; et al. (IEEE J. Solid State Circuits, 2015)