An 8-b 85-MS/s parallel pipeline A/D converter in 1- mu m CMOS. - Cormac S. G. Conroy; David W. Cline; Paul R. Gray (IEEE J. Solid State Circuits, 1993)

A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter in 1.2 μm CMOS. - David W. Cline; Paul R. Gray (IEEE J. Solid State Circuits, 1996)

A CMOS HDSL2 analog front-end. - Amit Gattani; David W. Cline; Paul J. Hurst; Paul M. Mosinskis (IEEE J. Solid State Circuits, 2000)