The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs. - Michael B. Taylor; Jason Sungtae Kim; Jason E. Miller; David Wentzlaff; Fae Ghodrat; Ben Greenwald; Henry Hoffmann; Paul R. Johnson; Jae W. Lee; Walter Lee; Albert Ma; Arvind Saraf; et al. (IEEE Micro, 2002)

Energy characterization of a tiled architecture processor with on-chip networks. - Jason Sungtae Kim; Michael Bedford Taylor; Jason E. Miller; David Wentzlaff (ISLPED, 2003)

A Quantitative Comparison of Reconfigurable, Tiled, and Conventional Architectures on Bit-Level Computation. - David Wentzlaff; Anant Agarwal (FCCM, 2004)

Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams. - Michael B. Taylor; Walter Lee; Jason E. Miller; David Wentzlaff; Ian Bratt; Ben Greenwald; Henry Hoffmann; Paul R. Johnson; Jason Sungtae Kim; James Psota; Arvind Saraf; Nathan Shnidman; et al. (ISCA, 2004)

Constructing Virtual Architectures on a Tiled Processor. - David Wentzlaff; Anant Agarwal (CGO, 2006)

On-Chip Interconnection Architecture of the Tile Processor. - David Wentzlaff; Patrick Griffin; Henry Hoffmann; Liewei Bao; Bruce Edwards; Carl Ramey; Matthew Mattina; Chyi-Chang Miao; John F. Brown III; Anant Agarwal (IEEE Micro, 2007)

TILE64 - Processor: A 64-Core SoC with Mesh Interconnect. - Shane Bell; Bruce Edwards; John Amann; Rich Conlin; Kevin Joyce; Vince Leung; John MacKay; Mike Reif; Liewei Bao; John F. Brown III; Matthew Mattina; Chyi-Chang Miao; et al. (ISSCC, 2008)

Factored operating systems (fos): the case for a scalable operating system for multicores. - David Wentzlaff; Anant Agarwal (ACM SIGOPS Oper. Syst. Rev., 2009)

Tiled Multicore Processors. - Michael B. Taylor; Walter Lee; Jason E. Miller; David Wentzlaff; Ian Bratt; Ben Greenwald; Henry Hoffmann; Paul R. Johnson; Jason Sungtae Kim; James Psota; Arvind Saraf; Nathan Shnidman; et al. (Multicore Processors and Systems, 2009)

An operating system for multicore and clouds: mechanisms and implementation. - David Wentzlaff; Charles Gruenwald III; Nathan Beckmann; Kevin Modzelewski; Adam Belay; Lamia Youseff; Jason E. Miller; Anant Agarwal (SoCC, 2010)

Remote Store Programming. - Henry Hoffmann; David Wentzlaff; Anant Agarwal (HiPEAC, 2010)

The case for elastic operating system services in fos. - Lamia Youseff; Nathan Beckmann; Harshad Kasture; Charles Gruenwald III; David Wentzlaff; Anant Agarwal (DAC, 2012)

Configurable fine-grain protection for multicore processor virtualization. - David Wentzlaff; Christopher J. Jackson; Patrick Griffin; Anant Agarwal (ISCA, 2012)

Distributed data structure for factored operating systems. - David Wentzlaff (2012)

The sharing architecture: sub-core configurability for IaaS clouds. - Yanqi Zhou; David Wentzlaff (ASPLOS, 2014)

PriME: A parallel and distributed simulator for thousand-core chips. - Yaosheng Fu; David Wentzlaff (ISPASS, 2014)

Execution Drafting: Energy Efficiency through Computation Deduplication. - Michael McKeown; Jonathan Balkind; David Wentzlaff (MICRO, 2014)

Coherence domain restriction on large scale systems. - Yaosheng Fu; Tri Minh Nguyen 003; David Wentzlaff (MICRO, 2015)

MORC: a manycore-oriented compressed cache. - Tri Minh Nguyen 003; David Wentzlaff (MICRO, 2015)

OpenPiton: An Open Source Manycore Research Framework. - Jonathan Balkind; Michael McKeown; Yaosheng Fu; Tri Minh Nguyen 003; Yanqi Zhou; Alexey Lavrov; Mohammad Shahrad; Adi Fuchs; Samuel Payne; Xiaohua Liang; Matthew Matl; David Wentzlaff (ASPLOS, 2016)

Availability Knob: Flexible User-Defined Availability in the Cloud. - Mohammad Shahrad; David Wentzlaff (SoCC, 2016)

Piton: A 25-core academic manycore research processor. - Michael McKeown; Yaosheng Fu; Tri Minh Nguyen 003; Yanqi Zhou; Jonathan Balkind; Alexey Lavrov; Mohammad Shahrad; Samuel Payne; David Wentzlaff (Hot Chips Symposium, 2016)

CASH: Supporting IaaS Customers with a Sub-core Configurable Architecture. - Yanqi Zhou; Henry Hoffmann; David Wentzlaff (ISCA, 2016)

MITTS: Memory Inter-arrival Time Traffic Shaping. - Yanqi Zhou; David Wentzlaff (ISCA, 2016)

Incentivizing self-capping to increase cloud utilization. - Mohammad Shahrad; Cristian Klein; Liang Zheng 002; Mung Chiang; Erik Elmroth; David Wentzlaff (SoCC, 2017)

Towards Deploying Decommissioned Mobile Devices as Cheap Energy-Efficient Compute Nodes. - Mohammad Shahrad; David Wentzlaff (HotCloud, 2017)

Camouflage: Memory Traffic Shaping to Mitigate Timing Attacks. - Yanqi Zhou; Sameer Wagh; Prateek Mittal; David Wentzlaff (HPCA, 2017)

Architectural tradeoffs for biodegradable computing. - Ting-Jung Chang; Zhuozhi Yao; Paul J. Jackson; Barry P. Rand; David Wentzlaff (MICRO, 2017)

Acoustic Denial of Service Attacks on HDDs. - Mohammad Shahrad; Arsalan Mosenia; Liwei Song; Mung Chiang; David Wentzlaff; Prateek Mittal (CoRR, 2017)

Piton: A Manycore Processor for Multitenant Clouds. - Michael McKeown; Yaosheng Fu; Tri Minh Nguyen 003; Yanqi Zhou; Jonathan Balkind; Alexey Lavrov; Mohammad Shahrad; Samuel Payne; David Wentzlaff (IEEE Micro, 2017)

Acoustic Denial of Service Attacks on Hard Disk Drives. - Mohammad Shahrad; Arsalan Mosenia; Liwei Song; Mung Chiang; David Wentzlaff; Prateek Mittal (ASHES@CCS, 2018)

Power and Energy Characterization of an Open Source 25-Core Manycore Processor. - Michael McKeown; Alexey Lavrov; Mohammad Shahrad; Paul J. Jackson; Yaosheng Fu; Jonathan Balkind; Tri Minh Nguyen 003; Katie Lim; Yanqi Zhou; David Wentzlaff (HPCA, 2018)

Scaling Datacenter Accelerators with Compute-Reuse Architectures. - Adi Fuchs; David Wentzlaff (ISCA, 2018)

CABLE: A CAche-Based Link Encoder for Bandwidth-Starved Manycores. - Tri Minh Nguyen 003; Adi Fuchs; David Wentzlaff (MICRO, 2018)

PiCL: A Software-Transparent, Persistent Cache Log for Nonvolatile Main Memory. - Tri Minh Nguyen 003; David Wentzlaff (MICRO, 2018)

JuxtaPiton: Enabling Heterogeneous-ISA Research with RISC-V and SPARC FPGA Soft-cores. - Katie Lim; Jonathan Balkind; David Wentzlaff (FPGA, 2019)

The Accelerator Wall: Limits of Chip Specialization. - Adi Fuchs; David Wentzlaff (HPCA, 2019)

ComputeDRAM: In-Memory Compute Using Off-the-Shelf DRAMs. - Fei Gao 016; Georgios Tziantzioulis; David Wentzlaff (MICRO, 2019)

Architectural Implications of Function-as-a-Service Computing. - Mohammad Shahrad; Jonathan Balkind; David Wentzlaff (MICRO, 2019)

OpenPiton: an open source hardware platform for your research. - Jonathan Balkind; Michael McKeown; Yaosheng Fu; Tri Minh Nguyen 003; Yanqi Zhou; Alexey Lavrov; Mohammad Shahrad; Adi Fuchs; Samuel Payne; Xiaohua Liang; Matthew Matl; David Wentzlaff (Commun. ACM, 2019)

BYOC: A "Bring Your Own Core" Framework for Heterogeneous-ISA Research. - Jonathan Balkind; Katie Lim; Michael Schaffner; Fei Gao 016; Grigory Chirkov; Ang Li 011; Alexey Lavrov; Tri M. Nguyen 002; Yaosheng Fu; Florian Zaruba; Kunal Gulati; Luca Benini; et al. (ASPLOS, 2020)

Organic-Flow: An Open-Source Organic Standard Cell Library and Process Development Kit. - Ting-Jung Chang; Zhuozhi Yao; Barry P. Rand; David Wentzlaff (DATE, 2020)

Cycle-Free FPGA Routing Graphs. - Ang Li 011; David Wentzlaff (FPGA, 2020)

Automated Design of FPGAs Facilitated by Cycle-Free Routing. - Ang Li 011; Ting-Jung Chang; David Wentzlaff (FPL, 2020)

HyperTRIO: Hyper-Tenant Translation of I/O Addresses. - Alexey Lavrov; David Wentzlaff (ISCA, 2020)

Enabling Programmable Transport Protocols in High-Speed NICs. - Mina Tahmasbi Arashloo; Alexey Lavrov; Manya Ghobadi; Jennifer Rexford; David Walker 001; David Wentzlaff (NSDI, 2020)

Rethinking Class-Discrimination Based CNN Channel Pruning. - Yuchen Liu 002; David Wentzlaff; Sun-Yuan Kung (CoRR, 2020)

OpenPiton at 5: A Nexus for Open and Agile Hardware Design. - Jonathan Balkind; Ting-Jung Chang; Paul J. Jackson; Georgios Tziantzioulis; Ang Li 011; Fei Gao 016; Alexey Lavrov; Grigory Chirkov; Jinzheng Tu 001; Mohammad Shahrad; David Wentzlaff (IEEE Micro, 2020)

Burstable Instances for Clouds: Performance Modeling, Equilibrium Analysis, and Revenue Maximization. - Yuxuan Jiang 001; Mohammad Shahrad; David Wentzlaff; Danny H. K. Tsang; Carlee Joe-Wong (IEEE/ACM Trans. Netw., 2020)

AutoSVA: Democratizing Formal Verification of RTL Module Interactions. - Marcelo Orenes-Vera; Aninda Manocha; David Wentzlaff; Margaret Martonosi (DAC, 2021)

PRGA: An Open-Source FPGA Research and Prototyping Framework. - Ang Li 011; David Wentzlaff (FPGA, 2021)

Evolving Transferable Pruning Functions. - Yuchen Liu 002; Sun-Yuan Kung; David Wentzlaff (CoRR, 2021)

Evolving transferable neural pruning functions. - Yuchen Liu 002; Sun-Yuan Kung; David Wentzlaff (GECCO, 2022)

Class-Discriminative CNN Compression. - Yuchen Liu 002; David Wentzlaff; Sun-Yuan Kung (ICPR, 2022)

Tiny but mighty: designing and realizing scalable latency tolerance for manycore SoCs. - Marcelo Orenes-Vera; Aninda Manocha; Jonathan Balkind; Fei Gao 016; Juan L. Aragón; David Wentzlaff; Margaret Martonosi (ISCA, 2022)

FracDRAM: Fractional Values in Off-the-Shelf DRAM. - Fei Gao 016; Georgios Tziantzioulis; David Wentzlaff (MICRO, 2022)

OPDB: A Scalable and Modular Design Benchmark. - Georgios Tziantzioulis; Ting-Jung Chang; Jonathan Balkind; Jinzheng Tu 001; Fei Gao 016; David Wentzlaff (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

SMAPPIC: Scalable Multi-FPGA Architecture Prototype Platform in the Cloud. - Grigory Chirkov; David Wentzlaff (ASPLOS (2), 2023)

CIFER: A 12nm, 16mm2, 22-Core SoC with a 1541 LUT6/mm2 1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA. - Ting-Jung Chang; Ang Li 011; Fei Gao 016; Tuan Ta; Georgios Tziantzioulis; Yanghui Ou; Moyang Wang; Jinzheng Tu 001; Kaifeng Xu; Paul J. Jackson; August Ning; Grigory Chirkov; et al. (CICC, 2023)

DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET. - Fei Gao 016; Ting-Jung Chang; Ang Li 011; Marcelo Orenes-Vera; Davide Giri; Paul J. Jackson; August Ning; Georgios Tziantzioulis; Joseph Zuckerman; Jinzheng Tu 001; Kaifeng Xu; Grigory Chirkov; et al. (CICC, 2023)

Duet: Creating Harmony between Processors and Embedded FPGAs. - Ang Li 011; August Ning; David Wentzlaff (HPCA, 2023)

Dalorex: A Data-Local Program Execution and Architecture for Memory-bound Applications. - Marcelo Orenes-Vera; Esin Tureci; David Wentzlaff; Margaret Martonosi (HPCA, 2023)

Seizing the Bandwidth Scaling of On-Package Interconnect in a Post-Moore's Law World. - Grigory Chirkov; David Wentzlaff (ICS, 2023)

Supply Chain Aware Computer Architecture. - August Ning; Georgios Tziantzioulis; David Wentzlaff (ISCA, 2023)

Building Efficient Neural Prefetcher. - Yuchen Liu 002; Georgios Tziantzioulis; David Wentzlaff (MEMSYS, 2023)

AutoCC: Automatic Discovery of Covert Channels in Time-Shared Hardware. - Marcelo Orenes-Vera; Hyunsung Yun; Nils Wistoff; Gernot Heiser; Luca Benini; David Wentzlaff; Margaret Martonosi (MICRO, 2023)

Duet: Creating Harmony between Processors and Embedded FPGAs. - Ang Li; August Ning; David Wentzlaff (CoRR, 2023)

Massive Data-Centric Parallelism in the Chiplet Era. - Marcelo Orenes-Vera; Esin Tureci; David Wentzlaff; Margaret Martonosi (CoRR, 2023)

Using LLMs to Facilitate Formal Verification of RTL. - Marcelo Orenes-Vera; Margaret Martonosi; David Wentzlaff (CoRR, 2023)

DCRA: A Distributed Chiplet-based Reconfigurable Architecture for Irregular Applications. - Marcelo Orenes-Vera; Esin Tureci; Margaret Martonosi; David Wentzlaff (CoRR, 2023)

Tascade: Hardware Support for Atomic-free, Asynchronous and Efficient Reduction Trees. - Marcelo Orenes-Vera; Esin Tureci; David Wentzlaff; Margaret Martonosi (CoRR, 2023)

A Hardware Evaluation Framework for Large Language Model Inference. - Hengrui Zhang; August Ning; Rohan Baskar Prabhakar; David Wentzlaff (CoRR, 2023)

LLMCompass: Enabling Efficient Hardware Design for Large Language Model Inference. - Hengrui Zhang; August Ning; Rohan Baskar Prabhakar; David Wentzlaff (ISCA, 2024)

MuchiSim: A Simulation Framework for Design Exploration of Multi-Chip Manycore Systems. - Marcelo Orenes-Vera; Esin Tureci; Margaret Martonosi; David Wentzlaff (ISPASS, 2024)

MindPalace: A Framework for Studying Microarchitecture Design of Function-as-a-Service. - Kaifeng Xu; Georgios Tziantzioulis; David Wentzlaff (ISPASS, 2024)

LUCIE: A Universal Chiplet-Interposer Design Framework for Plug-and-Play Integration. - Zixi Li; David Wentzlaff (MICRO, 2024)

Kraken: Inherently Parallel Transformers For Efficient Multi-Device Inference. - Rohan Baskar Prabhakar; Hengrui Zhang; David Wentzlaff (NeurIPS, 2024)

Chip Architectures Under Advanced Computing Sanctions✱. - August Ning; David Wentzlaff (ISCA, 2025)

Evaluation of MindPalace for Chip Design Tradeoffs on Function-as-a-Service. - Kaifeng Xu; Georgios Tziantzioulis; David Wentzlaff (ISPASS, 2025)

Optically Connected Multi-Stack HBM Modules for Large Language Model Training and Inference. - Yanghui Ou; Hengrui Zhang; Austin Rovinski; David Wentzlaff; Christopher Batten (IEEE Comput. Archit. Lett., 2025)