Temperature-Robust Performance Yield through Supply Voltage Selection. - David Wolpert 001; Paul Ampadu (ISCAS, 2007)

A Low-Power Safety Mode for Variation Tolerant Systems-on-Chip. - David Wolpert 001; Paul Ampadu (DFT, 2008)

Normal and Reverse Temperature Dependence in Variation-Tolerant Nanoscale Systems with High-k Dielectrics and Metal Gates. - David Wolpert 001; Paul Ampadu (NanoNet, 2008)

Adaptive Delay Correction for Runtime Variation in Dynamic voltage Scaling Systems. - David Wolpert 001; Paul Ampadu (J. Circuits Syst. Comput., 2008)

A Sensor to Detect Normal or Reverse Temperature Dependence in Nanoscale CMOS Circuits. - David Wolpert 001; Paul Ampadu (DFT, 2009)

Ballistic Deflection Transistors and the Emerging Nanoscale Era. - David Wolpert 001; Hiroshi Irie; Roman Sobolewski; Paul Ampadu; Quentin Diduck; Martin Margala (ISCAS, 2009)

Lookahead-based adaptive voltage scheme for energy-efficient on-chip interconnect links. - Bo Fu 002; David Wolpert 001; Paul Ampadu (NOCS, 2009)

A simulator for ballistic nanostructures in a 2-D electron gas. - Dennis Huo; Qiaoyan Yu; David Wolpert 001; Paul Ampadu (ACM J. Emerg. Technol. Comput. Syst., 2009)

Temperature-Aware Delay Borrowing for Energy-Efficient Low-Voltage Link Design. - David Wolpert 001; Bo Fu 002; Paul Ampadu (NOCS, 2010)

Self-Adaptive System for Addressing Permanent Errors in On-Chip Interconnects. - Teijo Lehtonen; David Wolpert 001; Pasi Liljeberg; Juha Plosila; Paul Ampadu (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Adaptive Voltage Control for Energy-Efficient NoC Links. - Paul Ampadu; Bo Fu 002; David Wolpert 001; Qiaoyan Yu (Low Power Networks-on-Chip, 2011)

A Sensor System to Detect Positive and Negative Current-Temperature Dependences. - David Wolpert 001; Paul Ampadu (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

Exploiting Programmable Temperature Compensation Devices to Manage Temperature-Induced Delay Uncertainty. - David Wolpert 001; Paul Ampadu (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

IBM z14™: 14nm microprocessor for the next-generation mainframe. - Christopher J. Berry; James D. Warnock; John Isakson; John Badar; Brian Bell 001; Frank Malgioglio; Guenter Mayer; Dina Hamid; Jesse Surprise; David Wolpert 001; Ofer Geva; Bill Huott; et al. (ISSCC, 2018)

IBM z14 design methodology enhancements in the 14-nm technology node. - Christopher J. Berry; James D. Warnock; John Badar; Dean G. Bair; Erwin Behnen; Brian Bell 001; Alper Buyuktosunoglu; Chris Cavitt; Pierce Chuang; Ofer Geva; Dina Hamid; John Isakson; et al. (IBM J. Res. Dev., 2018)

IBM z14: Enabling physical design in 14-nm technology for high-performance, high-reliability microprocessors. - David Wolpert 001; Erwin Behnen; Leon J. Sigal; Yuen H. Chan; Gustavo Enrique Téllez; Douglas Bradley; Richard E. Serton; Rajesh Veerabhadraiah; William Ansley; Andrew Bianchi; Nagu Dhanwada; Sungjae Lee; et al. (IBM J. Res. Dev., 2018)

IBM z14: Processor Characterization and Power Management for High-Reliability Mainframe Systems. - Christopher J. Berry; David Wolpert 001; Christos Vezyrtzis; Richard F. Rizzolo; Sean M. Carey; Yaniv Maroz; Hunter F. Shi; Dureseti Chidambarrao; Christian Jacobi 002; Anthony Saporito; Thomas Strach; Alper Buyuktosunoglu; et al. (IEEE J. Solid State Circuits, 2019)

2.7 IBM z15: A 12-Core 5.2GHz Microprocessor. - Christopher J. Berry; Brian Bell 001; Adam Jatkowski; Jesse Surprise; John Isakson; Ofer Geva; Brian Deskin; Mark Cichanowski; Dina Hamid; Chris Cavitt; Gregory Fredeman; Anthony Saporito; et al. (ISSCC, 2020)

IBM z15: Physical design improvements to significantly increase content in the same technology. - Christopher J. Berry; David Wolpert 001; Brian Bell 001; Adam Jatkowski; Jesse Surprise; Gerald Strevig; John Isakson; Ofer Geva; Brian Deskin; Mark Cichanowski; Giora Biran; Dina Hamid; et al. (IBM J. Res. Dev., 2020)

Cores, Cache, Content, and Characterization: IBM's Second Generation 14-nm Product, z15. - David Wolpert 001; Christopher J. Berry; Brian Bell 001; Adam Jatkowski; Jesse Surprise; John Isakson; Ofer Geva; Brian Deskin; Mark Cichanowski; Dina Hamid; Chris Cavitt; Gregory Fredeman; et al. (IEEE J. Solid State Circuits, 2021)

IBM Telum: a 16-Core 5+ GHz DCM. - Ofer Geva; Christopher J. Berry; Robert J. Sonnelitter; David Wolpert 001; Adam Collura; Thomas Strach; Di Phan; Cédric Lichtenau; Alper Buyuktosunoglu; Hubert Harrer; Jeffrey A. Zitz; Chad Marquart; et al. (ISSCC, 2022)

POWER10™: A 16-Core SMT8 Server Processor With 2TB/s Off-Chip Bandwidth in 7nm Technology. - Rahul M. Rao; Christopher J. Gonzalez; Eric Fluhr; Abraham Mathews; Andrew Bianchi; Daniel Dreps; David Wolpert 001; Eric Lai; Gerald Strevig; Glen A. Wiedemeier; Philipp Salz; Ryan Kruse (ISSCC, 2022)

37.1 IBM Telum II Processor Design-Technology Co-Optimizations for Power, Performance, Area, and Reliability. - David Wolpert 001; Gerry Strevig; Christopher J. Berry; Leon J. Sigal; Bill Huott; Mark Cichanowski; Matthias Pflanz; Tobias Werner 001; Philipp Salz; Nick Jinq; Michael Romain; Iris Leefken; et al. (ISSCC, 2025)

2.2 IBM Telum II: Next Generation 5.5GHz Microprocessor with On-Die Data Processing Unit and Improved AI Accelerator. - Gerald Strevig; Christopher J. Berry; Rahul M. Rao; Noam Jungmann; Michael A. Sperling; Michael J. Becht; Eduard Herkel; Matthias Pflanz; Patrick J. Meaney; Michael Romain; Mark Cichanowski; Amanda Venton; et al. (ISSCC, 2025)