Implementation of the PRESENT-80 block cipher and analysis of its vulnerability to Side Channel Attacks Exploiting Static Power. - Davide Bellizia; Giuseppe Scotti; Alessandro Trifiletti (MIXDES, 2016)

On-chip analog current equalizer as a countermeasure against side-channel attacks in CMOS nanometer technology. - Davide Bellizia; Giuseppe Scotti; Alessandro Trifiletti (MIXDES, 2016)

Multivariate Analysis Exploiting Static Power on Nanoscale CMOS Circuits for Cryptographic Applications. - Milena Djukanovic; Davide Bellizia; Giuseppe Scotti; Alessandro Trifiletti (AFRICACRYPT, 2017)

Novel measurements setup for attacks exploiting static power using DC pico-ammeter. - Davide Bellizia; Danilo Cellucci; Valerio Di Stefano; Giuseppe Scotti; Alessandro Trifiletti (ECCTD, 2017)

VHDL implementation of FWL RLS algorithm. - Davide Bellizia; Pietro Monsurrò; Alessandro Trifiletti (ECCTD, 2017)

Template attacks exploiting static power and application to CMOS lightweight crypto-hardware. - Davide Bellizia; Milena Djukanovic; Giuseppe Scotti; Alessandro Trifiletti (Int. J. Circuit Theory Appl., 2017)

Univariate Power Analysis Attacks Exploiting Static Dissipation of Nanometer CMOS VLSI Circuits for Cryptographic Applications. - Davide Bellizia; Simone Bongiovanni; Pietro Monsurrò; Giuseppe Scotti; Alessandro Trifiletti (IEEE Trans. Emerg. Top. Comput., 2017)

Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies. - Giuseppe Scotti; Davide Bellizia; Alessandro Trifiletti; Gaetano Palumbo (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Demonstrating an LPPN Processor. - Dina Kamel; Davide Bellizia; François-Xavier Standaert; Denis Flandre; David Bol (ASHES@CCS, 2018)

Secure Implementation of TEL-compatible Flip-Flops using a Standard-Cell Approach. - Davide Bellizia; Giuseppe Scotti; Alessandro Trifiletti (ISCAS, 2018)

A Novel Very Low Voltage Topology to implement MCML XOR Gates. - Davide Bellizia; Gaetano Palumbo; Giuseppe Scotti; Alessandro Trifiletti (PRIME, 2018)

TEL Logic Style as a Countermeasure Against Side-Channel Attacks: Secure Cells Library in 65nm CMOS and Experimental Results. - Davide Bellizia; Giuseppe Scotti; Alessandro Trifiletti (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Secure Double Rate Registers as an RTL Countermeasure Against Power Analysis Attacks. - Davide Bellizia; Simone Bongiovanni; Pietro Monsurrò; Giuseppe Scotti; Alessandro Trifiletti; Francesco Bruno Trotta (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Reducing a Masked Implementation's Effective Security Order with Setup Manipulations And an Explanation Based on Externally-Amplified Couplings. - Itamar Levi; Davide Bellizia; François-Xavier Standaert (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019)

A Systematic Appraisal of Side Channel Evaluation Strategies. - Melissa Azouaoui; Davide Bellizia; Ileana Buhan; Nicolas Debande; Sébastien Duval; Christophe Giraud 001; Éliane Jaulmes; François Koeune; Elisabeth Oswald; François-Xavier Standaert; Carolyn Whitnall (IACR Cryptol. ePrint Arch., 2020)

Mode-Level vs. Implementation-Level Physical Security in Symmetric Cryptography: A Practical Guide Through the Leakage-Resistance Jungle. - Davide Bellizia; Olivier Bronchain; Gaëtan Cassiers; Vincent Grosso; Chun Guo 002; Charles Momin; Olivier Pereira; Thomas Peters; François-Xavier Standaert (IACR Cryptol. ePrint Arch., 2020)

Beyond algorithmic noise or how to shuffle parallel implementations? - Itamar Levi; Davide Bellizia; François-Xavier Standaert (Int. J. Circuit Theory Appl., 2020)

SC-DDPL: A Novel Standard-Cell Based Approach for Counteracting Power Analysis Attacks in the Presence of Unbalanced Routing. - Davide Bellizia; Simone Bongiovanni; Mauro Olivieri; Giuseppe Scotti (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Ask Less, Get More: Side-Channel Signal Hiding, Revisited. - Itamar Levi; Davide Bellizia; David Bol; François-Xavier Standaert (IEEE Trans. Circuits Syst., 2020)

Spook: Sponge-Based Leakage-Resistant Authenticated Encryption with a Masked Tweakable Block Cipher. - Davide Bellizia; Francesco Berti; Olivier Bronchain; Gaëtan Cassiers; Sébastien Duval; Chun Guo 002; Gregor Leander; Gaëtan Leurent; Itamar Levi; Charles Momin; Olivier Pereira; Thomas Peters; et al. (IACR Trans. Symmetric Cryptol., 2020)

Towards a Better Understanding of Side-Channel Analysis Measurements Setups. - Davide Bellizia; Balazs Udvarhelyi; François-Xavier Standaert (CARDIS, 2021)

Post-Quantum Cryptography: Challenges and Opportunities for Robust and Secure HW Design. - Davide Bellizia; Nadia El Mrabet; Apostolos P. Fournaris; Simon Pontié; Francesco Regazzoni 001; François-Xavier Standaert; Élise Tasso; Emanuele Valea (DFT, 2021)

SC-DDPL as a Countermeasure against Static Power Side-Channel Attacks. - Davide Bellizia; Riccardo Della Sala; Giuseppe Scotti (Cryptogr., 2021)

A Novel Ultra-Compact FPGA PUF: The DD-PUF. - Riccardo Della Sala; Davide Bellizia; Giuseppe Scotti (Cryptogr., 2021)

Side-channel analysis of a learning parity with physical noise processor. - Dina Kamel; Davide Bellizia; Olivier Bronchain; François-Xavier Standaert (J. Cryptogr. Eng., 2021)

Learning Parity with Physical Noise: Imperfections, Reductions and FPGA Prototype. - Davide Bellizia; Clément Hoffmann; Dina Kamel; Hanlin Liu; Pierrick Méaux; François-Xavier Standaert; Yu Yu 001 (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021)

Tight-ES-TRNG: Improved Construction and Robustness Analysis. - Itamar Levi; Davide Bellizia; François-Xavier Standaert (SN Comput. Sci., 2022)

High-Throughput FPGA-Compatible TRNG Architecture Exploiting Multistimuli Metastable Cells. - Riccardo Della Sala; Davide Bellizia; Giuseppe Scotti (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Novel Ultra-Compact FPGA-Compatible TRNG Architecture Exploiting Latched Ring Oscillators. - Riccardo Della Sala; Davide Bellizia; Giuseppe Scotti (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Lightweight FPGA Compatible Weak-PUF Primitive Based on XOR Gates. - Riccardo Della Sala; Davide Bellizia; Giuseppe Scotti (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

When Bad News Become Good News Towards Usable Instances of Learning with Physical Errors. - Davide Bellizia; Clément Hoffmann; Dina Kamel; Pierrick Méaux; François-Xavier Standaert (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022)

An In-Depth Evaluation of Externally Amplified Coupling (EAC) Attacks - A Concrete Threat for Masked Cryptographic Implementations. - Ofek Gur; Tomer Gross; Davide Bellizia; François-Xavier Standaert; Itamar Levi (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Unveiling the True Power of the Latched Ring Oscillator for a Unified PUF and TRNG Architecture. - Riccardo Della Sala; Davide Bellizia; Giuseppe Scotti (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Exploiting Body-Driven Feedbacks in Physical Unclonable Functions for Ultra Low Voltage, Ultra Low Power Applications: A 0.3 V Weak-PUF. - Riccardo Della Sala; Davide Bellizia; Francesco Centurelli; Giuseppe Scotti; Alessandro Trifiletti (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)