Low Power Error Resilient Encoding for On-Chip Data Buses. - Davide Bertozzi; Luca Benini; Giovanni De Micheli (DATE, 2002)

Legacy SystemC Co-Simulation of Multi-Processor Systems-on-Chip. - Luca Benini; Davide Bertozzi; Davide Bruni; Nicola Drago; Franco Fummi; Massimo Poncino (ICCD, 2002)

Energy-efficient and reliable low-swing signaling for on-chip buses based on redundant coding. - Davide Bertozzi; Luca Benini; Bruno Riccò (ISCAS (1), 2002)

Parametric timing and power macromodels for high level simulation of low-swing interconnects. - Davide Bertozzi; Luca Benini; Bruno Riccò (ISLPED, 2002)

Power aware network interface management for streaming multimedia. - Davide Bertozzi; Luca Benini; Bruno Riccò (WCNC, 2002)

Energy-Reliability trade-Off for NoCs. - Davide Bertozzi; Luca Benini; Giovanni De Micheli (Networks on Chip, 2003)

Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems. - Davide Bertozzi; Anand Raghunathan; Luca Benini; Srivaths Ravi 001 (DATE, 2003)

xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs. - Matteo Dall'Osso; Gianluca Biccari; Luca Giovannini; Davide Bertozzi; Luca Benini (ICCD, 2003)

SystemC Cosimulation and Emulation of Multiprocessor SoC Designs. - Luca Benini; Davide Bertozzi; Davide Bruni; Nicola Drago; Franco Fummi; Massimo Poncino (Computer, 2003)

Performance Analysis of Arbitration Policies for SoC Communication Architectures. - Francesco Poletti; Davide Bertozzi; Luca Benini; Alessandro Bogliolo (Des. Autom. Embed. Syst., 2003)

Energy-Efficient Network-On-Chip Design. - Davide Bertozzi; Luca Benini; Giovanni De Micheli (Ultra Low-Power Electronics and Design, 2004)

Analyzing On-Chip Communication in a MPSoC Environment. - Mirko Loghi; Federico Angiolini; Davide Bertozzi; Luca Benini; Roberto Zafalon (DATE, 2004)

Network On-Chip Design for Gigascale Systems-on-Chip. - Davide Bertozzi; Luca Benini; Giovanni De Micheli (The Industrial Information Technology Handbook, 2005)

xpipes Lite: A Synthesis Oriented Design Library For Networks on Chips. - Stergios Stergiou; Federico Angiolini; Salvatore Carta; Luigi Raffo; Davide Bertozzi; Giovanni De Micheli (DATE, 2005)

Application-Specific Power-Aware Workload Allocation for Voltage Scalable MPSoC Platforms. - Martino Ruggiero; Andrea Acquaviva; Davide Bertozzi; Luca Benini (ICCD, 2005)

Allocation and Scheduling for MPSoCs via decomposition and no-good generation. - Luca Benini; Davide Bertozzi; Alessio Guerri; Michela Milano (IJCAI, 2005)

Fault tolerance overhead in network-on-chip flow control schemes. - Antonio Pullini; Federico Angiolini; Davide Bertozzi; Luca Benini (SBCCI, 2005)

Measuring Efficiency and Executability of Allocation and Scheduling in Multi-Processor Systems-on-Chip. - Luca Benini; Davide Bertozzi; Alessio Guerri; Michela Milano; Francesco Poletti (Intelligenza Artificiale, 2005)

Error control schemes for on-chip communication links: the energy-reliability tradeoff. - Davide Bertozzi; Luca Benini; Giovanni De Micheli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip. - Davide Bertozzi; Antoine Jalabert; Srinivasan Murali; Rutuparna Tamhankar; Stergios Stergiou; Luca Benini; Giovanni De Micheli (IEEE Trans. Parallel Distributed Syst., 2005)

MPARM: Exploring the Multi-Processor SoC Design Space with SystemC. - Luca Benini; Davide Bertozzi; Alessandro Bogliolo; Francesco Menichelli; Mauro Olivieri (J. VLSI Signal Process., 2005)

Network-on-Chip Design for Gigascale Systems-on-Chip. - Luca Benini; Davide Bertozzi; Giovanni De Micheli (Embedded Systems Handbook, 2005)

State-of-the-Art SoC Communication Architectures. - Davide Bertozzi; Luca Benini; Marisa López-Vallejo; José L. Ayala (Embedded Systems Handbook, 2005)

MPSoC ECG biochip: a multiprocessor system-on-chip for real-time human heart monitoring and analysis. - Iyad Al Khatib; Davide Bertozzi; Francesco Poletti; Luca Benini; Axel Jantsch; Mohamed Bechara; Hasan Khalifeh; Mazen Hajjar; Rustam Nabiev; Sven Jonsson (Conf. Computing Frontiers, 2006)

Allocation, Scheduling and Voltage Scaling on Energy Aware MPSoCs. - Luca Benini; Davide Bertozzi; Alessio Guerri; Michela Milano (CPAIOR, 2006)

A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: architectural design space exploration. - Iyad Al Khatib; Francesco Poletti; Davide Bertozzi; Luca Benini; Mohamed Bechara; Hasan Khalifeh; Axel Jantsch; Rustam Nabiev (DAC, 2006)

Supporting task migration in multi-processor systems-on-chip: a feasibility study. - Stefano Bertozzi; Andrea Acquaviva; Davide Bertozzi; Antonio Poggiali (DATE, 2006)

Communication-aware allocation and scheduling framework for stream-oriented multi-processor systems-on-chip. - Martino Ruggiero; Alessio Guerri; Davide Bertozzi; Francesco Poletti; Michela Milano (DATE, 2006)

A Cooperative, Accurate Solving Framework for Optimal Allocation, Scheduling and Frequency Selection on Energy-Efficient MPSoCs. - Martino Ruggiero; Pari Gioia; Guerri Alessio; Luca Benini; Michela Milano; Davide Bertozzi; Alexandru Andrei (SoC, 2006)

Performance analysis and design space exploration for high-end biomedical applications: challenges and solutions. - Iyad Al Khatib; Davide Bertozzi; Axel Jantsch; Luca Benini (CODES+ISSS, 2007)

Interactive presentation: Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms. - Simone Medardoni; Martino Ruggiero; Davide Bertozzi; Luca Benini; Giovanni Strano; Carlo Pistritto (DATE, 2007)

Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies. - Simone Medardoni; Davide Bertozzi; Enrico Macii (ISLPED, 2007)

Control and datapath decoupling in the design of a NoC switch: area, power and performance implications. - Simone Medardoni; Davide Bertozzi; Luca Benini; Enrico Macii (SoC, 2007)

Energy-Efficient Multiprocessor Systems-on-Chip for Embedded Computing: Exploring Programming Models and Their Architectural Support. - Francesco Poletti; Antonio Poggiali; Davide Bertozzi; Luca Benini; Pol Marchal; Mirko Loghi; Massimo Poncino (IEEE Trans. Computers, 2007)

Hardware/Software Architecture for Real-Time ECG Monitoring and Analysis Leveraging MPSoC Technology. - Iyad Al Khatib; Davide Bertozzi; Francesco Poletti; Luca Benini; Axel Jantsch; Mohamed Bechara; Hasan Khalifeh; Mazen Hajjar; Rustam Nabiev; Sven Jonsson (Trans. High Perform. Embed. Archit. Compil., 2007)

Networks-on-Chip: Emerging Research Topics and Novel Ideas. - Davide Bertozzi; Shashi Kumar; Maurizio Palesi (VLSI Design, 2007)

Variation tolerant NoC design by means of self-calibrating links. - Simone Medardoni; Marcello Lajolo; Davide Bertozzi (DATE, 2008)

Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style. - Bonesi Stefano; Davide Bertozzi; Luca Benini; Enrico Macii (DATE, 2008)

Network Interface Sharing Techniques for Area Optimized NoC Architectures. - Alberto Ferrante; Simone Medardoni; Davide Bertozzi (DSD, 2008)

Resource Management Policy Handling Multiple Use-Cases in MPSoC Platforms Using Constraint Programming. - Luca Benini; Davide Bertozzi; Michela Milano (ICLP, 2008)

Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework. - Francisco Gilabert Villamón; Simone Medardoni; Davide Bertozzi; Luca Benini; María Engracia Gómez; Pedro López 001; José Duato (NOCS, 2008)

A Fast and Accurate Technique for Mapping Parallel Applications on Stream-Oriented MPSoC Platforms with Communication Awareness. - Martino Ruggiero; Alessio Guerri; Davide Bertozzi; Michela Milano; Luca Benini (Int. J. Parallel Program., 2008)

A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: ECG prototype architectural design space exploration. - Iyad Al Khatib; Francesco Poletti; Davide Bertozzi; Luca Benini; Mohamed Bechara; Hasan Khalifeh; Axel Jantsch; Rustam Nabiev (ACM Trans. Design Autom. Electr. Syst., 2008)

SoC Communication Architectures: From Interconnection Buses to Packet-Switched NoCs. - José L. Ayala; Marisa López-Vallejo; Davide Bertozzi; Luca Benini (Embedded Systems Design and Verification, 2009)

Networks-on-Chip: an Interconnect Fabric for Multiprocessor Systems-on-Chip. - Francisco Gilabert Villamón; Davide Bertozzi; Luca Benini; Giovanni De Micheli (Embedded Systems Design and Verification, 2009)

Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints. - Francisco Gilabert Villamón; Daniele Ludovici; Simone Medardoni; Davide Bertozzi; Luca Benini; Georgi Nedeltchev Gaydadjiev (CISIS, 2009)

Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints. - Daniele Ludovici; Francisco Gilabert Villamón; Simone Medardoni; Crispín Gómez Requena; María Engracia Gómez; Pedro López 001; Georgi Nedeltchev Gaydadjiev; Davide Bertozzi (DATE, 2009)

Effectiveness of adaptive supply voltage and body bias as post-silicon variability compensation techniques for full-swing and low-swing on-chip communication channels. - Giacomo Paci; Davide Bertozzi; Luca Benini (DATE, 2009)

Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip. - Daniele Ludovici; Georgi Nedeltchev Gaydadjiev; Davide Bertozzi; Luca Benini (ACM Great Lakes Symposium on VLSI, 2009)

Yield-oriented evaluation methodology of network-on-chip routing implementations. - Samuel Rodrigo; Carles Hernández 001; José Flich; Federico Silla; José Duato; Simone Medardoni; Davide Bertozzi; Andres Mejia; Donglai Dai (SoC, 2009)

Flexible DOR routing for virtualization of multicore chips. - Tor Skeie; Frank Olaf Sem-Jacobsen; Samuel Rodrigo; José Flich; Davide Bertozzi; Simone Medardoni (SoC, 2009)

Architecture design principles for the integration of synchronization interfaces into Network-on-Chip switches. - Daniele Ludovici; Alessandro Strano; Davide Bertozzi (NoCArc@MICRO, 2009)

Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture. - Daniele Ludovici; Alessandro Strano; Davide Bertozzi; Luca Benini; Georgi Gaydadjiev (NOCS, 2009)

Networks on chips [editorial]. - Davide Bertozzi; Kees Goossens (IET Comput. Digit. Tech., 2009)

Efficient implementation of distributed routing algorithms for NoCs. - Samuel Rodrigo; Simone Medardoni; José Flich; Davide Bertozzi; José Duato (IET Comput. Digit. Tech., 2009)

Reducing the Abstraction and Optimality Gaps in the Allocation and Scheduling for Variable Voltage/Frequency MPSoC Platforms. - Martino Ruggiero; Davide Bertozzi; Luca Benini; Michela Milano; Alexandru Andrei (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs. - Daniele Ludovici; Alessandro Strano; Georgi Nedeltchev Gaydadjiev; Luca Benini; Davide Bertozzi (DATE, 2010)

Process variation and layout mismatch tolerant design of source synchronous links for GALS networks-on-chip. - Alessandro Strano; Carles Hernández 001; Federico Silla; Davide Bertozzi (SoC, 2010)

Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology. - Daniele Ludovici; Georgi Nedeltchev Gaydadjiev; Francisco Gilabert Villamón; María Engracia Gómez; Davide Bertozzi (NoCArc@MICRO, 2010)

Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing. - Samuel Rodrigo; José Flich; Antoni Roca 001; Simone Medardoni; Davide Bertozzi; Jesús Camacho Villanueva; Federico Silla; José Duato (NOCS, 2010)

Improved Utilization of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-processor Systems-on-Chip. - Francisco Gilabert Villamón; María Engracia Gómez; Simone Medardoni; Davide Bertozzi (NOCS, 2010)

A library of dual-clock FIFOs for cost-effective and flexible MPSoC design. - Alessandro Strano; Daniele Ludovici; Davide Bertozzi (ICSAMOS, 2010)

Exploiting structural redundancy of SIMD accelerators for their built-in self-testing/diagnosis and reconfiguration. - Alessandro Strano; Davide Bertozzi; Arnaud Grasset; Sami Yehia (ASAP, 2011)

Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture. - Alessandro Strano; Crispín Gómez Requena; Daniele Ludovici; Michele Favalli; María Engracia Gómez; Davide Bertozzi (DATE, 2011)

Mesochronous NoC technology for power-efficient GALS MPSoCs. - Daniele Ludovici; Alessandro Strano; Georgi Nedeltchev Gaydadjiev; Davide Bertozzi (INA-OCMC@HiPEAC, 2011)

Abstract modelling of switching elements for optical networks-on-chip with technology platform awareness. - Alberto Parini; Luca Ramini; Gaetano Bellanca; Davide Bertozzi (INA-OCMC@HiPEAC, 2011)

Bringing Network-on-Chip links to 45nm. - Marco Ferraresi; Giuseppina Gobbo; Daniele Ludovici; Davide Bertozzi (SoC, 2011)

Moonrake chip - GALS demonstrator in 40 nm CMOS technology. - Milos Krstic; Xin Fan 003; Eckhard Grass; Christoph Heer; Birgit Sanders; Luca Benini; Mohammad Reza Kakoee; Alessandro Strano; Davide Bertozzi (SoC, 2011)

Contrasting multi-synchronous MPSoC design styles for fine-grained clock domain partitioning: the full-HD video playback case study. - Hervé Tatenguem; Daniele Ludovici; Alessandro Strano; Davide Bertozzi; Helmut Reinig (NoCArc@MICRO, 2011)

System-level infrastructure for boot-time testing and configuration of networks-on-chip with programmable routing logic. - Alberto Ghiribaldi; Daniele Ludovici; Michele Favalli; Davide Bertozzi (VLSI-SoC, 2011)

Nonvolatile Memory Partitioning Scheme for Technology-Based Performance-Reliability Tradeoff. - Cristian Zambelli; Davide Bertozzi; Andrea Chimenton; Piero Olivo (IEEE Embed. Syst. Lett., 2011)

Variability compensation for full-swing against low-swing on-chip communication. - Giacomo Paci; Davide Bertozzi; Luca Benini (IET Comput. Digit. Tech., 2011)

Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip Design. - Alessandro Strano; Carles Hernández 001; Federico Silla; Davide Bertozzi (Int. J. Embed. Real Time Commun. Syst., 2011)

Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems. - Samuel Rodrigo; José Flich; Antoni Roca 001; Simone Medardoni; Davide Bertozzi; Jesús Camacho Villanueva; Federico Silla; José Duato (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Non-intrusive trace & debug noc architecture with accurate timestamping for GALS SoCs. - Vladimir Todorov; Alberto Ghiribaldi; Helmut Reinig; Davide Bertozzi; Ulf Schlichtmann (CODES+ISSS, 2012)

Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCs. - José L. Abellán; Juan Fernández Peinador; Manuel E. Acacio; Davide Bertozzi; Daniele Bortolotti; Andrea Marongiu; Luca Benini (DATE, 2012)

A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories. - Cristian Zambelli; Marco Indaco; Michele Fabiano; Stefano Di Carlo; Paolo Prinetto; Piero Olivo; Davide Bertozzi (DATE, 2012)

Cost-Effective Contention Avoidance in a CMP with Shared Memory Controllers. - Samuel Rodrigo; Frank Olaf Sem-Jacobsen; Hervé Tatenguem; Tor Skeie; Davide Bertozzi (Euro-Par, 2012)

Power efficiency of switch architecture extensions for fault tolerant NoC design. - Alberto Ghiribaldi; Alessandro Strano; Michele Favalli; Davide Bertozzi (IGCC, 2012)

Quest for the ultimate network-on-chip: the NaNoC project. - Alessandro Strano; Davide Bertozzi; Federico Angiolini; Leonardo Di G. Gregorio; Frank Olaf Sem-Jacobsen; Vladimir Todorov; José Flich; José Silla; Tobias Bjerregaard (INA-OCMC@HiPEAC, 2012)

Optimizing built-in pseudo-random self-testing for network-on-chip switches. - Simone Terenzi; Alessandro Strano; Davide Bertozzi (INA-OCMC@HiPEAC, 2012)

A retrospective look at xpipes: The exciting ride from a design experience to a design platform for nanoscale networks-on-chip. - Davide Bertozzi; Luca Benini (ICCD, 2012)

Ultra-low latency NoC testing via pseudo-random test pattern compaction. - Hervé Tatenguem; Alessandro Strano; Vineeth Govind; Jaan Raik; Davide Bertozzi (ISSoC, 2012)

Cooperative Built-in Self-Testing and Self-Diagnosis of NoC Bisynchronous Channels. - Nicola Caselli; Alessandro Strano; Daniele Ludovici; Davide Bertozzi (MCSoC, 2012)

Power efficiency of wavelength-routed optical NoC topologies for global connectivity of 3D multi-core processors. - Luca Ramini; Davide Bertozzi (NoCArc@MICRO, 2012)

Engineering a Bandwidth-Scalable Optical Layer for a 3D Multi-core Processor with Awareness of Layout Constraints. - Luca Ramini; Davide Bertozzi; Luca P. Carloni (NOCS, 2012)

OSR-Lite: Fast and deadlock-free NoC reconfiguration framework. - Alessandro Strano; Davide Bertozzi; Francisco Triviño; José L. Sánchez 002; Francisco J. Alfaro; José Flich (ICSAMOS, 2012)

Evaluation of GALS Methods in Scaled CMOS Technology: Moonrake Chip Experience. - Milos Krstic; Xin Fan 003; Eckhard Grass; Luca Benini; Mohammad Reza Kakoee; Christoph Heer; Birgit Sanders; Alessandro Strano; Davide Bertozzi (Int. J. Embed. Real Time Commun. Syst., 2012)

A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems. - Alberto Ghiribaldi; Davide Bertozzi; Steven M. Nowick (DATE, 2013)

Contrasting wavelength-routed optical NoC topologies for power-efficient 3D-stacked multicore processors using physical-layer analysis. - Luca Ramini; Paolo Grani; Sandro Bartolini; Davide Bertozzi (DATE, 2013)

Topic 13: High-Performance Networks and Communication - (Introduction). - Olav Lysne; Torsten Hoefler; Pedro López 001; Davide Bertozzi (Euro-Par, 2013)

A fast algorithm for runtime reconfiguration to maximize the lifetime of nanoscale NoCs. - Francisco Triviño; Davide Bertozzi; José Flich (INA-OCMC@HiPEAC, 2013)

PROTON: an automatic place-and-route tool for optical networks-on-chip. - Anja Boos; Luca Ramini; Ulf Schlichtmann; Davide Bertozzi (ICCAD, 2013)

Optimizing the overhead for network-on-chip routing reconfiguration in parallel multi-core platforms. - Marco Balboni; Francisco Triviño; José Flich; Davide Bertozzi (ISSoC, 2013)

System interconnect extensions for fully transparent demand paging in low-cost MMU-less embedded systems. - Lorenzo Zuolo; Gabriele Miorandi; Cristian Zambelli; Piero Olivo; Davide Bertozzi (ISSoC, 2013)

Optimising pseudo-random built-in self-testing of fully synchronous as well as multisynchronous networks-on-chip. - Alessandro Strano; Nicola Caselli; Simone Terenzi; Davide Bertozzi (IET Comput. Digit. Tech., 2013)

A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs. - Alberto Ghiribaldi; Daniele Ludovici; Francisco Triviño; Alessandro Strano; José Flich; José L. Sánchez 002; Francisco J. Alfaro; Michele Favalli; Davide Bertozzi (ACM Trans. Embed. Comput. Syst., 2013)

An efficient, low-cost routing framework for convex mesh partitions to support virtualization. - Frank Olaf Sem-Jacobsen; Samuel Rodrigo; Tor Skeie; Alessandro Strano; Davide Bertozzi (ACM Trans. Embed. Comput. Syst., 2013)

Enabling power efficiency through dynamic rerouting on-chip. - Frank Olaf Sem-Jacobsen; Samuel Rodrigo; Alessandro Strano; Tor Skeie; Davide Bertozzi; Francisco Gilabert Villamón (ACM Trans. Embed. Comput. Syst., 2013)

A vertically integrated and interoperable multi-vendor synthesis flow for predictable noc design in nanoscale technologies. - Alberto Ghiribaldi; Hervé Tatenguem Fankem; Federico Angiolini; Mikkel Bystrup Stensgaard; Tobias Bjerregaard; Davide Bertozzi (ASP-DAC, 2014)

Guided Participatory Research on Parallel Computer Architectures for K-12 Students Through a Narrative Approach. - Valentina Mazzoni; Luigina Mortari; Federico Corni; Davide Bertozzi (CSEDU (3), 2014)

Assessing the energy break-even point between an optical NoC architecture and an aggressive electronic baseline. - Luca Ramini; Alberto Ghiribaldi; Paolo Grani; Sandro Bartolini; Hervé Tatenguem Fankem; Davide Bertozzi (DATE, 2014)

SSDExplorer: A virtual platform for fine-grained design space exploration of Solid State Drives. - Lorenzo Zuolo; Cristian Zambelli; Rino Micheloni; Salvatore Galfano; Marco Indaco; Stefano Di Carlo; Paolo Prinetto; Piero Olivo; Davide Bertozzi (DATE, 2014)

Interdisciplinary design of a research experience on microelectronic systems for K-12 students. - Valentina Mazzoni; Davide Bertozzi (EWME, 2014)

A complete electronic network interface architecture for global contention-free communication over emerging optical networks-on-chip. - Marta Ortín-Obón; Luca Ramini; Hervé Tatenguem Fankem; Víctor Viñals; Davide Bertozzi (ACM Great Lakes Symposium on VLSI, 2014)

A feature-rich NoC switch with cross-feature optimizations for the next generation of reliable and reconfigurable embedded systems. - Alessandro Strano; Alberto Ghiribaldi; Hervé Tatenguem Fankem; Davide Bertozzi (INA-OCMC@HiPEAC, 2014)

Augmenting manycore programmable accelerators with photonic interconnect technology for the high-end embedded computing domain. - Marco Balboni; Marta Ortín-Obón; Alessandro Capotondi; Hervé Tatenguem Fankem; Alberto Ghiribaldi; Luca Ramini; Víctor Viñals; Andrea Marongiu; Davide Bertozzi (NOCS, 2014)

Crossbar replication vs. sharing for virtual channel flow control in asynchronous NoCs: A comparative study. - Gabriele Miorandi; Alberto Ghiribaldi; Steven M. Nowick; Davide Bertozzi (VLSI-SoC, 2014)

Capturing the sensitivity of optical network quality metrics to its network interface parameters. - Marta Ortín-Obón; Luca Ramini; Víctor Viñals; Davide Bertozzi (Concurr. Comput. Pract. Exp., 2014)

Editorial. - Davide Bertozzi; Giorgos Dimitrakopoulos; Sören Sonntag (Des. Autom. Embed. Syst., 2014)

FLARES: An Aging Aware Algorithm to Autonomously Adapt the Error Correction Capability in NAND Flash Memories. - Stefano Di Carlo; Salvatore Galfano; Marco Indaco; Paolo Prinetto; Davide Bertozzi; Piero Olivo; Cristian Zambelli (ACM Trans. Archit. Code Optim., 2014)

DyAFNoC: Dynamically Reconfigurable NoC Characterization Using a Simple Adaptive Deadlock-Free Routing Algorithm with a Low Implementation Cost. - Ernesto Villegas Castillo; Gabriele Miorandi; Davide Bertozzi; Jiang Chau Wang (ARC, 2015)

Increasing Impartiality and Robustness in High-Performance N-Way Asynchronous Arbiters. - Gabriele Miorandi; Davide Bertozzi; Steven M. Nowick (ASYNC, 2015)

Synergistic use of multiple on-chip networks for ultra-low latency and scalable distributed routing reconfiguration. - Marco Balboni; José Flich; Davide Bertozzi (DATE, 2015)

Partitioning Strategies of Wavelength-Routed Optical Networks-on-Chip for Laser Power Minimization. - Marta Ortín; Luca Ramini; Marco Balboni; Lorenzo Zuolo; Maddalena Nonato; Víctor Viñals; Davide Bertozzi (SiPhotonics@HiPEAC, 2015)

Contrasting Power Efficiency of Contention Resolution vs. Avoidance Strategies in Optical Ring Interconnects for Photonically-Integrated Embedded Systems. - Luca Ramini; Mahdi Tala; Davide Bertozzi (INA-OCMC@HiPEAC, 2015)

NoC-centric partitioning and reconfiguration technologies for the efficient sharing of multi-core programmable accelerators. - Marco Balboni; Davide Bertozzi (HPCS, 2015)

Dynamically Reconfigurable NoC using a deadlock-free flexible routing algorithm with a low hardware implementation cost. - Ernesto Villegas Castillo; Jiang Chau Wang; Gabriele Miorandi; Davide Bertozzi (LASCAS, 2015)

The fast evolving landscape of on-chip communication - Selected future challenges and research avenues. - Davide Bertozzi; Giorgos Dimitrakopoulos; José Flich; Sören Sonntag (Des. Autom. Embed. Syst., 2015)

SSDExplorer: A Virtual Platform for Performance/Reliability-Oriented Fine-Grained Design Space Exploration of Solid State Drives. - Lorenzo Zuolo; Cristian Zambelli; Rino Micheloni; Marco Indaco; Stefano Di Carlo; Paolo Prinetto; Davide Bertozzi; Piero Olivo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers. - Davide Bertozzi; Stefano Di Carlo; Salvatore Galfano; Marco Indaco; Piero Olivo; Paolo Prinetto; Cristian Zambelli (ACM Trans. Embed. Comput. Syst., 2015)

Evolutionary vs. Revolutionary Interconnect Technologies for Future Low-Power Multi-Core Systems. - Gabriele Miorandi; Mahdi Tala; Marco Balboni; Luca Ramini; Davide Bertozzi (AISTECS@HiPEAC, 2016)

Design technology for fault-free and maximally-parallel wavelength-routed optical networks-on-chip. - Andrea Peano; Luca Ramini; Marco Gavanelli; Maddalena Nonato; Davide Bertozzi (ICCAD, 2016)

A built-in self-testing framework for asynchronous bundled-data NoC switches resilient to delay variations. - Gabriele Miorandi; Alberto Celin; Michele Favalli; Davide Bertozzi (NOCS, 2016)

Populating and exploring the design space of wavelength-routed optical network-on-chip topologies by leveraging the add-drop filtering primitive. - Mahdi Tala; Marco Castellari; Marco Balboni; Davide Bertozzi (NOCS, 2016)

PROTON+: A Placement and Routing Tool for 3D Optical Networks-on-Chip with a Single Optical Layer. - Anja von Beuningen; Luca Ramini; Davide Bertozzi; Ulf Schlichtmann (ACM J. Emerg. Technol. Comput. Syst., 2016)

A tool for synthesizing power-efficient and custom-tailored wavelength-routed optical rings. - Marta Ortín-Obón; Luca Ramini; Víctor Viñals Yúfera; Davide Bertozzi (ASP-DAC, 2017)

Accurate Assessment of Bundled-Data Asynchronous NoCs Enabled by a Predictable and Efficient Hierarchical Synthesis Flow. - Gabriele Miorandi; Marco Balboni; Steven M. Nowick; Davide Bertozzi (ASYNC, 2017)

An asynchronous NoC router in a 14nm FinFET library: Comparison to an industrial synchronous counterpart. - Weiwei Jiang 002; Davide Bertozzi; Gabriele Miorandi; Steven M. Nowick; Wayne P. Burleson; Greg Sadowski (DATE, 2017)

Transparent lifetime built-in self-testing of networks-on-chip through the selective non-concurrent testing of their communication channels. - Marco Balboni; Davide Bertozzi (AISTECS@HiPEAC, 2017)

Concurrent network-on-chip lifetime testing through selective disconnection of its communication channels. - Marco Balboni; Davide Bertozzi (NEWCAS, 2017)

Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Networks-on-Chip. - Davide Bertozzi; Gabriele Miorandi; Mahdi Tala; Steven M. Nowick (NGCAS, 2017)

Propelling breakthrough embedded microprocessors by means of integrated photonics. - Davide Bertozzi; Sébastien Rumley (SoCC, 2017)

Logic programming approaches for routing fault-free and maximally parallel wavelength-routed optical networks-on-chip (Application paper). - Marco Gavanelli; Maddalena Nonato; Andrea Peano; Davide Bertozzi (Theory Pract. Log. Program., 2017)

Contrasting Laser Power Requirements of Wavelength-Routed Optical NoC Topologies Subject to the Floorplanning, Placement, and Routing Constraints of a 3-D-Stacked System. - Marta Ortín-Obón; Mahdi Tala; Luca Ramini; Víctor Viñals Yúfera; Davide Bertozzi (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A Boolean model for delay fault testing of emerging digital technologies based on ambipolar devices. - Marcello Dalpasso; Davide Bertozzi; Michele Favalli (DATE, 2018)

Exploring the Performance-Energy Optimization Space of a Bridge Between 3D-Stacked Electronic and Optical Networks-on-Chip. - Mahdi Tala; Oliver Schrape; Milos Krstic; Davide Bertozzi (DCIS, 2018)

Wavelength-Routed Optical Networks-on-Chip: Design Methods and Tools to Bridge the Gap Between Logic Topologies and Physical Ones in 3D Architectures. - Davide Bertozzi; Marco Gavanelli; Maddalena Nonato (ACM Great Lakes Symposium on VLSI, 2018)

Interfacing 3D-stacked Electronic and Optical NoCs with Mixed CMOS-ECL Bridges: a Realistic Preliminary Assessment. - Mahdi Tala; Oliver Schrape; Milos Krstic; Davide Bertozzi (ACM Great Lakes Symposium on VLSI, 2018)

CustomTopo: a topology generation method for application-specific wavelength-routed optical NoCs. - Mengchu Li; Tsun-Ming Tseng; Davide Bertozzi; Mahdi Tala; Ulf Schlichtmann (ICCAD, 2018)

Correlating Power Efficiency and Lifetime to Programming Strategies in RRAM-Based FPGAs. - Cristian Zambelli; Marco Castellari; Piero Olivo; Davide Bertozzi (NGCAS, 2018)

Understanding the Design Space of Wavelength-Routed Optical NoC Topologies for Power-Performance Optimization. - Mahdi Tala; Davide Bertozzi (VLSI-SoC, 2018)

Special session on overcoming reliability and energy-efficiency challenges with silicon photonics for future manycore computing. - Sudeep Pasricha; Davide Bertozzi; Hui Li 034 (VTS, 2018)

A network model for routing-fault-free wavelength selection in WRONoCs design. - Maddalena Nonato; Davide Bertozzi; Marco Gavanelli; Andrea Peano (Electron. Notes Discret. Math., 2018)

An Interconnect-Centric Approach to the Flexible Partitioning and Isolation of Many-Core Accelerators for Fog Computing. - Mariem Turki; Davide Bertozzi (DCIS, 2019)

A Low-Latency and Flexible TDM NoC for Strong Isolation in Security-Critical Systems. - Miguel Gorgues Alonso; José Flich; Meriem Turki; Davide Bertozzi (MCSoC, 2019)

Assessing the Configuration Space of the Open Source NVDLA Deep Learning Accelerator on a Mainstream MPSoC Platform. - Alessandro Veronesi; Davide Bertozzi; Milos Krstic (VLSI-SoC (Selected Papers), 2020)

Cross-Layer Hardware/Software Assessment of the Open-Source NVDLA Configurable Deep Learning Accelerator. - Alessandro Veronesi; Milos Krstic; Davide Bertozzi (VLSI-SOC, 2020)

PSION+: Combining Logical Topology and Physical Layout Optimization for Wavelength-Routed ONoCs. - Alexandre Truppel; Tsun-Ming Tseng; Davide Bertozzi; José Carlos Alves; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Comparative Analysis and Optimization of the SystemC-AMS Analog Simulation Efficiency of Resistive Crossbar Arrays. - Tommaso Rizzi; Emilio Pérez-Bosch Quesada; Christian Wenger; Cristian Zambelli; Davide Bertozzi (DCIS, 2021)

The Challenge of Classification Confidence Estimation in Dynamically-Adaptive Neural Networks. - Francesco Dall'Occo; Andrés Bueno-Crespo; José L. Abellán; Davide Bertozzi; Michele Favalli (SAMOS, 2021)

Reconfigurable on-chip wireless interconnections through optical phased arrays (Invited). - Giovanna Calò; Marina Barbiroli; Gaetano Bellanca; Davide Bertozzi; Franco Fuschini; Velio Tralli; Giovanni Serafino; Vincenzo Petruzzelli (SLIP, 2021)

Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Systems. - Davide Bertozzi; Gabriele Miorandi; Alberto Ghiribaldi; Wayne P. Burleson; Greg Sadowski; Kshitij Bhardwaj; Weiwei Jiang 002; Steven M. Nowick (IEEE Micro, 2021)

An Asynchronous Soft Macro for Ultra-Low Power Communication in Neuromorphic Computing. - Davide Bertozzi; Kshitij Bhardwaj; Steven M. Nowick (AICAS, 2022)

Exploring Software Models for the Resilience Analysis of Deep Learning Accelerators: the NVDLA Case Study. - Alessandro Veronesi; Francesco Dall'Occo; Davide Bertozzi; Michele Favalli; Milos Krstic (DDECS, 2022)

Integrated Optical Phased Arrays for on-Chip Communication. - M. Khalid; Giovanna Calò; Gaetano Bellanca; Jacopo Nanni; Marina Barbiroli; Franco Fuschini; Velio Tralli; Davide Bertozzi; Vincenzo Petruzzelli (ICTON, 2023)

Efficient Resource-Aware Neural Architecture Search with a Neuro-Symbolic Approach. - Elena Bellodi; Davide Bertozzi; Alice Bizzarri; Michele Favalli; Michele Fraccaroli; Riccardo Zese (MCSoC, 2023)

Technology-Aware Drift Resilience Analysis of RRAM Crossbar Array Configurations. - Daniel Reiser; Marc Reichenbach; Tommaso Rizzi; Andrea Baroni; Markus Fritscher; Christian Wenger; Cristian Zambelli; Davide Bertozzi (NEWCAS, 2023)

Adaptive Localization for Autonomous Racing Vehicles with Resource-Constrained Embedded Platforms. - Federico Gavioli; Gianluca Brilli; Paolo Burgio; Davide Bertozzi (DATE, 2024)

Cross-Layer Reliability Analysis of NVDLA Accelerators: Exploring the Configuration Space. - Alessandro Veronesi; Alessandro Nazzari; Dario Passarello; Milos Krstic; Michele Favalli; Luca Cassano; Antonio Miele; Davide Bertozzi; Cristiana Bolchini (ETS, 2024)

LNOI Wireless Switches Based on Optical Phased Arrays for On-Chip Communication. - Muhammad Khalid; Simone Ferraresi; Gaetano Bellanca; Marina Barbiroli; Franco Fuschini; Velio Tralli; Davide Bertozzi; Vincenzo Petruzzelli; Giovanna Calò (IEEE J. Sel. Areas Commun., 2024)

An Ultra-Low Cost and Multicast-Enabled Asynchronous NoC for Neuromorphic Edge Computing. - Zhe Su; Simone Ramini; Demetra Coffen Marcolin; Alessandro Veronesi; Milos Krstic; Giacomo Indiveri; Davide Bertozzi; Steven M. Nowick (IEEE J. Emerg. Sel. Topics Circuits Syst., 2024)

A Synthesis Toolflow for the Predictable Implementation of High-Performance Bundled-Data Asynchronous NoCs on FPGA. - Giuseppe Chessa; Elena Bellodi; Michele Favalli; Davide Zoni; Davide Bertozzi (ASYNC, 2025)

Multi-Partner Project: Twinning for Excellence in Reliable Electronics (TWIN-RELECT). - Marko S. Andjelkovic; Fabian Vargas 001; Milos Krstic; Luigi Dilillo; Alain Michez; Frederic Wrobel; Davide Bertozzi; Mikel Luján; Christos Georgakidis; Nikolaos Chatzivangelis; Katerina Tsilingiri; Nikolaos Zazatis; et al. (DATE, 2025)

An Efficient Multicast Addressing Encoding Scheme for Multi-Core Neuromorphic Processors. - Zhe Su; Aron Bencsik; Giacomo Indiveri; Davide Bertozzi (ISCAS, 2025)