A standard cell approach for MagnetoElastic NML circuits. - Davide Giri; Marco Vacca; Giovanni Causapruno; Wenjing Rao; Mariagrazia Graziano; Maurizio Zamboni (NANOARCH, 2014)

NoC-Based Support of Heterogeneous Cache-Coherence Models for Accelerators. - Davide Giri; Paolo Mantovani; Luca P. Carloni (NOCS, 2018)

Accelerators and Coherence: An SoC Perspective. - Davide Giri; Paolo Mantovani; Luca P. Carloni (IEEE Micro, 2018)

Parallel and Serial Computation in Nanomagnet Logic: An Overview. - Davide Giri; Giovanni Causapruno; Fabrizio Riente (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Runtime reconfigurable memory hierarchy in embedded scalable platforms. - Davide Giri; Paolo Mantovani; Luca P. Carloni (ASP-DAC, 2019)

Teaching Heterogeneous Computing with System-Level Design Methods. - Luca P. Carloni; Emilio G. Cota; Giuseppe Di Guglielmo; Davide Giri; Jihye Kwon; Paolo Mantovani; Luca Piccolboni; Michele Petracca (WCAE@ISCA, 2019)

HL5: A 32-bit RISC-V Processor Designed with High-Level Synthesis. - Paolo Mantovani; Robert Margelli; Davide Giri; Luca P. Carloni (CICC, 2020)

ESP4ML: Platform-Based Design of Systems-on-Chip for Embedded Machine Learning. - Davide Giri; Kuan-Lin Chiu; Giuseppe Di Guglielmo; Paolo Mantovani; Luca P. Carloni (DATE, 2020)

Agile SoC Development with Open ESP : Invited Paper. - Paolo Mantovani; Davide Giri; Giuseppe Di Guglielmo; Luca Piccolboni; Joseph Zuckerman; Emilio G. Cota; Michele Petracca; Christian Pilato; Luca P. Carloni (ICCAD, 2020)

MosaicSim: A Lightweight, Modular Simulator for Heterogeneous Systems. - Opeoluwa Matthews; Aninda Manocha; Davide Giri; Marcelo Orenes-Vera; Esin Tureci; Tyler Sorensen 001; Tae Jun Ham; Juan L. Aragón; Luca P. Carloni; Margaret Martonosi (ISPASS, 2020)

The MosaicSim Simulator (Full Technical Report). - Opeoluwa Matthews; Aninda Manocha; Davide Giri; Marcelo Orenes-Vera; Esin Tureci; Tyler Sorensen 001; Tae Jun Ham; Juan L. Aragón; Luca P. Carloni; Margaret Martonosi (CoRR, 2020)

Agile SoC Development with Open ESP. - Paolo Mantovani; Davide Giri; Giuseppe Di Guglielmo; Luca Piccolboni; Joseph Zuckerman; Emilio G. Cota; Michele Petracca; Christian Pilato; Luca P. Carloni (CoRR, 2020)

MasterMind: Many-Accelerator SoC Architecture for Real-Time Brain-Computer Interfaces. - Guy Eichler; Luca Piccolboni; Davide Giri; Luca P. Carloni (ICCD, 2021)

Cohmeleon: Learning-Based Orchestration of Accelerator Coherence in Heterogeneous SoCs. - Joseph Zuckerman; Davide Giri; Jihye Kwon; Paolo Mantovani; Luca P. Carloni (MICRO, 2021)

Applications and Techniques for Fast Machine Learning in Science. - Allison McCarn Deiana; Nhan Tran; Joshua Agar; Michaela Blott; Giuseppe Di Guglielmo; Javier M. Duarte; Philip C. Harris; Scott Hauck; Mia Liu; Mark S. Neubauer; Jennifer Ngadiuba; Seda Ogrenci Memik; et al. (CoRR, 2021)

Accelerator Integration for Open-Source SoC Design. - Davide Giri; Kuan-Lin Chiu; Guy Eichler; Paolo Mantovani; Luca P. Carloni (IEEE Micro, 2021)

Work-in-Progress: An Open-Source Platform for Design and Programming of Partially Reconfigurable Heterogeneous SoCs. - Biruk B. Seyoum; Davide Giri; Kuan-Lin Chiu; Luca P. Carloni (CASES, 2022)

A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC. - Tianyu Jia; Paolo Mantovani; Maico Cassel dos Santos; Davide Giri; Joseph Zuckerman; Erik Jens Loscalzo; Martin Cochet; Karthik Swaminathan; Gabriele Tombesi; Jeff Jun Zhang; Nandhini Chandramoorthy; John-David Wellman; et al. (ESSCIRC, 2022)

A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components. - Maico Cassel dos Santos; Tianyu Jia; Martin Cochet; Karthik Swaminathan; Joseph Zuckerman; Paolo Mantovani; Davide Giri; Jeff Jun Zhang; Erik Jens Loscalzo; Gabriele Tombesi; Kevin Tien; Nandhini Chandramoorthy; et al. (ICCAD, 2022)

Accelerators & Security: The Socket Approach. - Luca Piccolboni; Davide Giri; Luca P. Carloni (IEEE Comput. Archit. Lett., 2022)

Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESP. - Joseph Zuckerman; Paolo Mantovani; Davide Giri; Luca P. Carloni (CoRR, 2022)

DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET. - Fei Gao 016; Ting-Jung Chang; Ang Li 011; Marcelo Orenes-Vera; Davide Giri; Paul J. Jackson; August Ning; Georgios Tziantzioulis; Joseph Zuckerman; Jinzheng Tu 001; Kaifeng Xu; Grigory Chirkov; et al. (CICC, 2023)

PR-ESP: An Open-Source Platform for Design and Programming of Partially Reconfigurable SoCs. - Biruk B. Seyoum; Davide Giri; Kuan-Lin Chiu; Bryce Natter; Luca P. Carloni (DATE, 2023)

An Analysis of Accelerator Data-Transfer Modes in NoC-Based SoC Architectures. - Kuan-Lin Chiu; Davide Giri; Luca Piccolboni; Luca P. Carloni (HPEC, 2023)

A 12nm 18.1TFLOPs/W Sparse Transformer Processor with Entropy-Based Early Exit, Mixed-Precision Predication and Fine-Grained Power Management. - Thierry Tambe; Jeff Zhang 001; Coleman Hooper; Tianyu Jia; Paul N. Whatmough; Joseph Zuckerman; Maico Cassel dos Santos; Erik Jens Loscalzo; Davide Giri; Kenneth L. Shepard; Luca P. Carloni; Alexander M. Rush; et al. (ISSCC, 2023)

SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs. - Gabriele Tombesi; Joseph Zuckerman; Paolo Mantovani; Davide Giri; Maico Cassel dos Santos; Tianyu Jia; David Brooks 001; Gu-Yeon Wei; Luca P. Carloni (IEEE Des. Test, 2023)

Mozart: Taming Taxes and Composing Accelerators with Shared-Memory. - Vignesh Suresh; Bakshree Mishra; Ying Jing; Zeran Zhu; Naiyin Jin; Charles Block; Paolo Mantovani; Davide Giri; Joseph Zuckerman; Luca P. Carloni; Sarita V. Adve (PACT, 2024)

BlitzCoin: Fully Decentralized Hardware Power Management for Accelerator-Rich SoCs. - Martin Cochet; Karthik Swaminathan; Erik Jens Loscalzo; Joseph Zuckerman; Maico Cassel dos Santos; Davide Giri; Alper Buyuktosunoglu; Tianyu Jia; David Brooks 001; Gu-Yeon Wei; Kenneth L. Shepard; Luca P. Carloni; et al. (ISCA, 2024)

14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration. - Maico Cassel dos Santos; Tianyu Jia; Joseph Zuckerman; Martin Cochet; Davide Giri; Erik Jens Loscalzo; Karthik Swaminathan; Thierry Tambe; Jeff Jun Zhang; Alper Buyuktosunoglu; Kuan-Lin Chiu; Giuseppe Di Guglielmo; et al. (ISSCC, 2024)

A 400-ns-Settling- Time Hybrid Dynamic Voltage Frequency Scaling Architecture and Its Application in a 22-Core Network-on-Chip SoC in 12-nm FinFET Technology. - Erik Jens Loscalzo; Martin Cochet; Joseph Zuckerman; Samira Zalias; Michael Lekas; Stephen Cahill; Tianyu Jia; Karthik Swaminathan; Maico Cassel dos Santos; Davide Giri; Hesam Sadeghi; Joseph Meyer; et al. (VLSI Technology and Circuits, 2024)