A Low-Overhead Heuristic for Mixed Workload Resource Partitioning in Cluster-Based Architectures. - Davide Zoni; Patrick Bellasi; William Fornaciari (ARCS, 2012)

Consolidation of multi-tier workloads with performance and reliability constraints. - Andrea Sansottera; Davide Zoni; Paolo Cremonesi; William Fornaciari (HPCS, 2012)

HANDS: heterogeneous architectures and networks-on-chip design and simulation. - Davide Zoni; Simone Corbetta; William Fornaciari (ISLPED, 2012)

Thermal/performance trade-off in network-on-chip architectures. - Davide Zoni; Simone Corbetta; William Fornaciari (ISSoC, 2012)

A Temperature and Reliability Oriented Simulation Framework for Multi-core Architectures. - Simone Corbetta; Davide Zoni; William Fornaciari (ISVLSI, 2012)

Towards energy-efficient functional configuration in WSNs. - Carlo Brandolese; William Fornaciari; Luigi Rucco; Davide Zoni (PDeS, 2012)

A sensor-less NBTI mitigation methodology for NoC architectures. - Davide Zoni; William Fornaciari (SoCC, 2012)

Sensor-wise methodology to face NBTI stress of NoC buffers. - Davide Zoni; William Fornaciari (DATE, 2013)

NBTI-aware design of NoC buffers. - Davide Zoni; William Fornaciari (INA-OCMC@HiPEAC, 2013)

A cycle accurate simulation framework for asynchronous NoC design. - Federico Terraneo; Davide Zoni; William Fornaciari (ISSoC, 2013)

Adaptive routing and Dynamic Frequency Scaling for NoC power-performance optimizations. - Davide Zoni; José Flich; William Fornaciari (PATMOS, 2013)

An analytical, dynamic, power-performance router model for run-time NoC optimizations. - Davide Zoni; Federico Terraneo; William Fornaciari (SoCC, 2013)

Exploring power reliability and performance aspects in on-chip networks for multi-cores. - Davide Zoni (2014)

The MANGO FET-HPC Project: An Overview. - José Flich; Giovanni Agosta; Philipp Ampletzer; David Atienza Alonso; Alessandro Cilardo; William Fornaciari; Mario Kovac; Fabrice Roudet; Davide Zoni (CSE, 2015)

TEST: Assessing NoC Policies Facing Aging and Leakage Power. - Davide Zoni; Luca Borghese; Giuseppe Massari; Simone Libutti; William Fornaciari (DSD, 2015)

An accurate simulation framework for thermal explorations and optimizations. - Federico Terraneo; Davide Zoni; William Fornaciari (RAPIDO@HiPEAC, 2015)

Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators. - Davide Zoni; William Fornaciari (ACM J. Emerg. Technol. Comput. Syst., 2015)

A control-based methodology for power-performance optimization in NoCs exploiting DVFS. - Davide Zoni; Federico Terraneo; William Fornaciari (J. Syst. Archit., 2015)

Enabling HPC for QoS-sensitive applications: The MANGO approach. - José Flich; Giovanni Agosta; Philipp Ampletzer; David Atienza Alonso; Carlo Brandolese; Alessandro Cilardo; William Fornaciari; Ynse Hoornenborg; Mario Kovac; Bruno Maitre; Giuseppe Massari; Hrvoje Mlinaric; et al. (DATE, 2016)

CUTBUF: Buffer Management and Router Design for Traffic Mixing in VNET-Based NoCs. - Davide Zoni; José Flich; William Fornaciari (IEEE Trans. Parallel Distributed Syst., 2016)

A DVFS Cycle Accurate Simulation Framework with Asynchronous NoC Design for Power-Performance Optimizations. - Davide Zoni; Federico Terraneo; William Fornaciari (J. Signal Process. Syst., 2016)

MANGO: Exploring Manycore Architectures for Next-GeneratiOn HPC Systems. - José Flich; Giovanni Agosta; Philipp Ampletzer; David Atienza Alonso; Carlo Brandolese; Etienne Cappe; Alessandro Cilardo; Leon Dragic; Alexandre Dray; Alen Duspara; William Fornaciari; Gerald Guillaume; et al. (DSD, 2017)

DENA: A DVFS-Capable Heterogeneous NoC Architecture. - Luca Cremona; William Fornaciari; Andrea Marchese; Michele Zanella; Davide Zoni (ISVLSI, 2017)

BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers. - Davide Zoni; Andrea Canidio; William Fornaciari; Panayiotis Englezakis; Chrysostomos Nicopoulos; Yiannakis Sazeides (J. Parallel Distributed Comput., 2017)

CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties. - Kim Grüttner; Ralph Görgen; Sören Schreiner; Fernando Herrera; Pablo Peñil; Julio L. Medina; Eugenio Villar; Gianluca Palermo; William Fornaciari; Carlo Brandolese; Davide Gadioli; Emanuele Vitali; et al. (Microprocess. Microsystems, 2017)

Towards Fine-Grained DVFS in Embedded Multi-core CPUs. - Giuseppe Massari; Federico Terraneo; Michele Zanella; Davide Zoni (ARCS, 2018)

PowerProbe: Run-time power modeling through automatic RTL instrumentation. - Davide Zoni; Luca Cremona; William Fornaciari (DATE, 2018)

Fast Estimations of Failure Probability Over Long Time Spans. - Michail Noltsis; Panayiotis Englezakis; Eleni Maragkoudaki; Chrysostomos Nicopoulos; Dimitrios Rodopoulos; Francky Catthoor; Yiannakis Sazeides; Davide Zoni; Dimitrios Soudris (NANOARCH, 2018)

Reliable power and time-constraints-aware predictive management of heterogeneous exascale systems. - William Fornaciari; Giovanni Agosta; David Atienza; Carlo Brandolese; Leila Cammoun; Luca Cremona; Alessandro Cilardo; Albert Farrés; José Flich; Carles Hernández 001; Michal Kulchewski; Simone Libutti; et al. (SAMOS, 2018)

Exploring manycore architectures for next-generation HPC systems through the MANGO approach. - José Flich; Giovanni Agosta; Philipp Ampletzer; David Atienza Alonso; Carlo Brandolese; Etienne Cappe; Alessandro Cilardo; Leon Dragic; Alexandre Dray; Alen Duspara; William Fornaciari; Edoardo Fusella; et al. (Microprocess. Microsystems, 2018)

PowerTap: All-digital power meter modeling for run-time power monitoring. - Davide Zoni; Luca Cremona; Alessandro Cilardo; Mirko Gagliardi; William Fornaciari (Microprocess. Microsystems, 2018)

DarkCache: Energy-Performance Optimization of Tiled Multi-Cores by Adaptively Power-Gating LLC Banks. - Davide Zoni; Luca Colombo; William Fornaciari (ACM Trans. Archit. Code Optim., 2018)

A Comprehensive Side-Channel Information Leakage Analysis of an In-Order RISC CPU Microarchitecture. - Davide Zoni; Alessandro Barenghi; Gerardo Pelosi; William Fornaciari (ACM Trans. Design Autom. Electr. Syst., 2018)

Evaluating the Trade-offs in the Hardware Design of the LEDAcrypt Encryption Functions. - Alessandro Barenghi; William Fornaciari; Andrea Galimberti; Gerardo Pelosi; Davide Zoni (ICECS, 2019)

Partial Packet Forwarding to Improve Performance in Fully Adaptive Routing for Cache-Coherent NoCs. - Tamer Ahmed Eltaras; William Fornaciari; Davide Zoni (PDP, 2019)

Analysis and countermeasures to side-channel attacks: a hardware design perspective. - Davide Zoni (ReCoSoC, 2019)

Integrating Side Channel Security in the FPGA Hardware Design Flow. - Alessandro Barenghi; Matteo Brevi; William Fornaciari; Gerardo Pelosi; Davide Zoni (COSADE, 2020)

VGM-Bench: FPU Benchmark Suite for Computer Vision, Computer Graphics and Machine Learning Applications. - Luca Cremona; William Fornaciari; Andrea Galimberti; Andrea Romanoni; Davide Zoni (SAMOS, 2020)

Flexible and Scalable FPGA-Oriented Design of Multipliers for Large Binary Polynomials. - Davide Zoni; Andrea Galimberti; William Fornaciari (IEEE Access, 2020)

Efficient and Scalable FPGA-Oriented Design of QC-LDPC Bit-Flipping Decoders for Post-Quantum Cryptography. - Davide Zoni; Andrea Galimberti; William Fornaciari (IEEE Access, 2020)

All-Digital Energy-Constrained Controller for General-Purpose Accelerators and CPUs. - Davide Zoni; Luca Cremona; William Fornaciari (IEEE Embed. Syst. Lett., 2020)

All-Digital Control-Theoretic Scheme to Optimize Energy Budget and Allocation in Multi-Cores. - Davide Zoni; Luca Cremona; William Fornaciari (IEEE Trans. Computers, 2020)

Scramble Suit: A Profile Differentiation Countermeasure to Prevent Template Attacks. - Alessandro Barenghi; William Fornaciari; Gerardo Pelosi; Davide Zoni (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

TEXTAROSSA: Towards EXtreme scale Technologies and Accelerators for euROhpc hw/Sw Supercomputing Applications for exascale. - Giovanni Agosta; Daniele Cattaneo 002; William Fornaciari; Andrea Galimberti; Giuseppe Massari; Federico Reghenzani; Federico Terraneo; Davide Zoni; Carlo Brandolese; Massimo Celino; Francesco Iannone; Paolo Palazzari; et al. (DSD, 2021)

Automatic identification and hardware implementation of a resource-constrained power model for embedded systems. - Luca Cremona; William Fornaciari; Davide Zoni (Sustain. Comput. Informatics Syst., 2021)

An FPU design template to optimize the accuracy-efficiency-area trade-off. - Davide Zoni; Andrea Galimberti; William Fornaciari (Sustain. Comput. Informatics Syst., 2021)

On the use of hardware accelerators in QC-MDPC code-based cryptography. - Andrea Galimberti; Davide Galli; Gabriele Montanaro; William Fornaciari; Davide Zoni (CF, 2022)

FPGA implementation of BIKE for quantum-resistant TLS. - Andrea Galimberti; Davide Galli; Gabriele Montanaro; William Fornaciari; Davide Zoni (DSD, 2022)

Hardware-Software Co-Design of BIKE with HLS-Generated Accelerators. - Gabriele Montanaro; Andrea Galimberti; Ernesto Colizzi; Davide Zoni (ICECS 2022, 2022)

On the Effectiveness of True Random Number Generators Implemented on FPGAs. - Davide Galli; Andrea Galimberti; William Fornaciari; Davide Zoni (SAMOS, 2022)

Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators. - Nicolás Landeros Muñoz; Alejandro Valero; Ruben Gran Tejero; Davide Zoni (J. Syst. Archit., 2022)

Cost-effective fixed-point hardware support for RISC-V embedded systems. - Davide Zoni; Andrea Galimberti (J. Syst. Archit., 2022)

Efficient and Scalable FPGA Design of GF($2^m$2m) Inversion for Post-Quantum Cryptosystems. - Andrea Galimberti; Gabriele Montanaro; Davide Zoni (IEEE Trans. Computers, 2022)

Design of Side-Channel-Resistant Power Monitors. - Davide Zoni; Luca Cremona; William Fornaciari (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Towards EXtreme scale technologies and accelerators for euROhpc hw/Sw supercomputing applications for exascale: The TEXTAROSSA approach. - Giovanni Agosta; Marco Aldinucci; Carlos Álvarez 001; Roberto Ammendola; Yasir Arfat; Olivier Beaumont; Massimo Bernaschi; Andrea Biagioni; Tommaso Boccali; Bérenger Bramas; Carlo Brandolese; Barbara Cantalupo; et al. (Microprocess. Microsystems, 2022)

Hardware and Software Support for Mixed Precision Computing: a Roadmap for Embedded and HPC Systems. - William Fornaciari; Giovanni Agosta; Daniele Cattaneo 002; Lev Denisov; Andrea Galimberti; Gabriele Magnani; Davide Zoni (DATE, 2023)

An Evaluation of the State-Of-The-Art Software and Hardware Implementations of BIKE. - Andrea Galimberti; Gabriele Montanaro; William Fornaciari; Davide Zoni (PARMA-DITAM, 2023)

Dynamic Power Consumption of the Full Posit Processing Unit: Analysis and Experiments. - Michele Piccoli; Davide Zoni; William Fornaciari; Giuseppe Massari; Marco Cococcioni; Federico Rossi 003; Sergio Saponara; Emanuele Ruffaldi (PARMA-DITAM, 2023)

HLS-based acceleration of the BIKE post-quantum KEM on embedded-class heterogeneous SoCs. - Andrea Galimberti; Gabriele Montanaro; Davide Zoni (ICECS, 2023)

RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project. - William Fornaciari; Federico Reghenzani; Giovanni Agosta; Davide Zoni; Andrea Galimberti; Francesco Conti 001; Yvan Tortorella; Emanuele Parisi; Francesco Barchi; Andrea Bartolini; Andrea Acquaviva; Daniele Gregori; et al. (SAMOS, 2023)

A Survey on Run-time Power Monitors at the Edge. - Davide Zoni; Andrea Galimberti; William Fornaciari (ACM Comput. Surv., 2023)

A Deep- Learning Technique to Locate Cryptographic Operations in Side-Channel Traces. - Giuseppe Chiari; Davide Galli; Francesco Lattari; Matteo Matteucci; Davide Zoni (DATE, 2024)

The TEXTAROSSA Project: Cool all the Way Down to the Hardware. - Antonio Filgueras; Giovanni Agosta; Marco Aldinucci; Carlos Álvarez 001; Pasqua D'Ambra; Massimo Bernaschi; Andrea Biagioni; Daniele Cattaneo 002; Alessandro Celestini; Massimo Celino; Carlotta Chiarini; Francesca Lo Cicero; et al. (DSD, 2024)

Rethinking the Switch Architecture for Stateful In-network Computing. - Alberto Lerner; Davide Zoni; Paolo Costa; Gianni Antichi (HotNets, 2024)

Hound: Locating Cryptographic Primitives in Desynchronized Side-Channel Traces using Deep-Learning. - Davide Galli; Giuseppe Chiari; Davide Zoni (ICCD, 2024)

A Prototype-Based Framework to Design Scalable Heterogeneous SoCs with Fine-Grained DFS. - Gabriele Montanaro; Andrea Galimberti; Davide Zoni (ICCD, 2024)

A novel virtual prototyping methodology for timing-accurate simulation of AMS circuits. - Teo Vallone; Hayri Verner Hasou; Ernesto Colizzi; Sara Vinco; Davide Zoni (ISQED, 2024)

Functional ISS-Driven Verification of Superscalar RISC-V Processors. - Andrea Galimberti; Marco Vitali; Sebastiano Vittoria; Davide Zoni (CoRR, 2024)

Blink: Fast Automated Design of Run-Time Power Monitors on FPGA-Based Computing Platforms. - Andrea Galimberti; Michele Piccoli; Davide Zoni (CoRR, 2024)

The Impact of Run-Time Variability on Side-Channel Attacks Targeting FPGAs. - Davide Galli; Adriano Guarisco; William Fornaciari; Matteo Matteucci; Davide Zoni (CoRR, 2024)

Design-time methodology for optimizing mixed-precision CPU architectures on FPGA. - Lev Denisov; Andrea Galimberti; Daniele Cattaneo 002; Giovanni Agosta; Davide Zoni (J. Syst. Archit., 2024)

Dataset for: A Deep-Learning Technique to Locate Cryptographic Operations in Side-Channel Traces. - Giuseppe Chiari; Davide Galli; Francesco Lattari; Matteo Matteucci; Davide Zoni (Zenodo, 2024)

A Synthesis Toolflow for the Predictable Implementation of High-Performance Bundled-Data Asynchronous NoCs on FPGA. - Giuseppe Chessa; Elena Bellodi; Michele Favalli; Davide Zoni; Davide Bertozzi (ASYNC, 2025)

A Benchmarking Platform for DDR4 Memory Performance in Data-Center-Class FPGAs. - Andrea Galimberti; Gabriele Montanaro; Andrea Motta; Federico Proverbio; Davide Zoni (ISCAS, 2025)

Rabbit: Dynamic Clock Randomization to Protect against Side-Channel Attacks. - Davide Galli; Matteo Matteucci; Davide Zoni (ISCAS, 2025)

FARMER: An Online-Learning Driven Methodology for Workload Consolidation on Large FPGAs. - Gabriele Montanaro; Francesco Trovò; Davide Zoni (ISCAS, 2025)

Chameleon: A Dataset for Segmenting and Attacking Obfuscated Power Traces in Side-Channel Analysis. - Davide Galli; Giuseppe Chiari; Davide Zoni (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2025)

A Deep Learning-Assisted Template Attack Against Dynamic Frequency Scaling Countermeasures. - Davide Galli; Francesco Lattari; Matteo Matteucci; Davide Zoni (IEEE Trans. Computers, 2025)

An FPGA-Based Open-Source Hardware-Software Framework for Side-Channel Security Research. - Davide Zoni; Andrea Galimberti; Davide Galli (IEEE Trans. Computers, 2025)

Rhea: a Framework for Fast Design and Validation of RTL Cache-Coherent Memory Subsystems. - Davide Zoni; Andrea Galimberti; Adriano Guarisco (CoRR, 2025)