A 0.13µm CMOS ΔΣ PLL FM transmitter. - Ying Wu 003; Xiaodong Liu; Dawei Ye; Vijay Viswam; Lin Zhu; Ping Lu 002; Dejan Radjen; Henrik Sjöland (NORCHIP, 2011)

A wide bandwidth fractional-N synthesizer for LTE with phase noise cancellation using a hybrid-ΔΣ-DAC and charge re-timing. - Dawei Ye; Ping Lu 002; Pietro Andreani; Ronan A. R. van der Zee (ISCAS, 2013)

26.2 An Ultra-Low-Power receiver using transmitted-reference and shifted limiters for in-band interference resilience. - Dawei Ye; Ronan A. R. van der Zee; Bram Nauta (ISSCC, 2016)

A 915 MHz 175 µW Receiver Using Transmitted-Reference and Shifted Limiters for 50 dB In-Band Interference Tolerance. - Dawei Ye; Ronan A. R. van der Zee; Bram Nauta (IEEE J. Solid State Circuits, 2016)

A 13.56MHz Wireless Power and Data Transfer Receiver Achieving 75.4% Effective-Power-Conversion Efficiency with 0.1% ASK Modulation Depth and 9.2mW Output Power. - Yu Wang 046; Dawei Ye; Liangjian Lyu; Yingfei Xiang; Hao Min; Chuanjin Richard Shi (ISSCC, 2018)

A 340nW/Channel Neural Recording Analog Front-End using Replica-Biasing LNAs to Tolerate 200mVpp Interfere from 350mV Power Supply. - Liangjian Lyu; Dawei Ye; Chuanjin Richard Shi (ISCAS, 2019)

A 2.46GHz, -88dBm Sensitivity CMOS Passive Mixer-First Nonlinear Receiver with >50dB Tolerance to In-Band Interferer. - Dawei Ye; Rongjin Xu; Liangjian Lyu; Chuanjin Richard Shi (ISCAS, 2019)

A 2.4GHz 65nm CMOS Mixer-First Receiver Using 4-Stage Cascaded Inverter-Based Envelope-Biased LNAs Achieving 66dB In-Band Interference Tolerance and -83dBm Sensitivity. - Dawei Ye; Rongjin Xu; Chuanjin Richard Shi (ISSCC, 2019)

A 400 MHz, 8-Bit, 1.75-ps Resolution Pipelined-Two-Step Time-to-Digital Converter with Dynamic Time Amplification. - Yuting Tu; Rongjin Xu; Dawei Ye; Liangjian Lyu; Chuanjin Richard Shi (ISCAS, 2020)

A Wireless Power and Data Transfer Receiver Achieving 75.4% Effective Power Conversion Efficiency and Supporting 0.1% Modulation Depth for ASK Demodulation. - Dawei Ye; Yu Wang 046; Yingfei Xiang; Liangjian Lyu; Hao Min; Chuanjin Richard Shi (IEEE J. Solid State Circuits, 2020)

A 340 nW/Channel 110 dB PSRR Neural Recording Analog Front-End Using Replica-Biasing LNA, Level-Shifter Assisted PGA, and Averaged LFP Servo Loop in 65 nm CMOS. - Liangjian Lyu; Dawei Ye; Chuanjin Richard Shi (IEEE Trans. Biomed. Circuits Syst., 2020)

A Fully-Integrated 64-Channel Wireless Neural Interfacing SoC Achieving 110 dB AFE PSRR and Supporting 54 Mb/s Symbol Rate, Meter-Range Wireless Data Transmission. - Liangjian Lyu; Dawei Ye; Rongjin Xu; Geng Mu; Heng Zhao; Yingfei Xiang; Yuting Tu; Yiyun Zhang; Chuanjin Richard Shi (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A Two-Tone Wake-Up Receiver with an Envelope-Detector-First Architecture Using Envelope Biasing and Active Inductor Load Achieving 41/33dB In-Band Rejection to CW/AM Interference. - Dawei Ye; Yuting Tu; Wenjun Gong; Rongjin Xu; Chuanjin Richard Shi (A-SSCC, 2021)

An 8-Channel Analog Front-End with a PVT-lnsensitive Switched-Capacitor and Analog Combo DC Servo Loop Achieving 300mV Tolerance and 0.64s Recovery Time to Electrode-DC Offset for Physiological Signal Recording. - Geng Mu; Dawei Ye; Liangjian Lyu; Xiaobin Zhao; Chuanjin Richard Shi (CICC, 2021)

A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain. - Dawei Ye; Rongjin Xu; Chuanjin Richard Shi (IEEE J. Solid State Circuits, 2021)

A 0.021mm2 65nm CMOS 2.5GHz Digital Injection-Locked Clock Multiplier with Injection Pulse Shaping Achieving -79dBc Reference Spur and 0.496mW/GHz Power Efficiency. - Rongjin Xu; Dawei Ye; Sirou Li; Chuanjin Richard Shi (ISSCC, 2022)

A 2.0-2.9 GHz ring-based injection-locked clock multiplier using a self-alignment frequency-tracking loop for reference spur reduction. - Rongjin Xu; Dawei Ye; Chuanjin Richard Shi (Integr., 2022)

Erratum to "A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain". - Dawei Ye; Rongjin Xu; Chuanjin Richard Shi (IEEE J. Solid State Circuits, 2022)

Analysis and Design of Digital Injection-Locked Clock Multipliers Using Bang-Bang Phase Detectors. - Rongjin Xu; Dawei Ye; Chuanjin Richard Shi (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Echo State Network-Enabled Intelligent Smart Sensor Design for Creating a Robotic Nervous System. - Dawei Ye; Bingxin Cao; Weiping Zhou (Int. J. Pattern Recognit. Artif. Intell., 2023)