A Hybrid Approach to Equivalent Fault Identification for Verification Environment Qualification. - Chia-Cheng Wu; Tung-Yuan Lee; Yung-An Lai; Hsin-Pei Wang; De-Xuan Ji; Yan-Ping Chang; Teng-Chia Wang; Chin-Heng Liu; Chun-Yao Wang; Yung-Chih Chen (ACM Great Lakes Symposium on VLSI, 2018)

A Glitch Key-Gate for Logic Locking. - De-Xuan Ji; Hsiao-Yu Chiang; Chia-Chun Lin; Chia-Cheng Wu; Yung-Chih Chen; Chun-Yao Wang (SoCC, 2019)

LOOPLock: Logic Optimization-Based Cyclic Logic Locking. - Hsiao-Yu Chiang; Yung-Chih Chen; De-Xuan Ji; Xiang-Min Yang; Chia-Chun Lin; Chun-Yao Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)