A scanisland based design enabling prebond testability in die-stacked microprocessors. - Dean L. Lewis; Hsien-Hsin S. Lee (ITC, 2007)

Architectural evaluation of 3D stacked RRAM caches. - Dean L. Lewis; Hsien-Hsin S. Lee (3DIC, 2009)

Pre-bond testable low-power clock tree design for 3D stacked ICs. - Xin Zhao 001; Dean L. Lewis; Hsien-Hsin S. Lee; Sung Kyu Lim (ICCAD, 2009)

Testing Circuit-Partitioned 3D IC Designs. - Dean L. Lewis; Hsien-Hsin S. Lee (ISVLSI, 2009)

High Performance Non-blocking Switch Design in 3D Die-Stacking Technology. - Dean L. Lewis; Sudhakar Yalamanchili; Hsien-Hsin S. Lee (ISVLSI, 2009)

Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory. - Michael B. Healy; Krit Athikulwongse; Rohan Goel; Mohammad M. Hossain; Dae Hyun Kim 004; Young-Joon Lee; Dean L. Lewis; Tzu-Wei Lin; Chang Liu 034; Moongon Jung; Brian Ouellette; Mohit Pathak; et al. (CICC, 2010)

An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth. - Dong Hyuk Woo; Nak Hee Seong; Dean L. Lewis; Hsien-Hsin S. Lee (HPCA, 2010)

Designing 3D test wrappers for pre-bond and post-bond test of 3D embedded cores. - Dean L. Lewis; Shreepad Panth; Xin Zhao 001; Sung Kyu Lim; Hsien-Hsin S. Lee (ICCD, 2011)

Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs. - Xin Zhao 001; Dean L. Lewis; Hsien-Hsin S. Lee; Sung Kyu Lim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

3D-MAPS: 3D Massively parallel processor with stacked memory. - Dae Hyun Kim 004; Krit Athikulwongse; Michael B. Healy; Mohammad M. Hossain; Moongon Jung; Ilya Khorosh; Gokul Kumar; Young-Joon Lee; Dean L. Lewis; Tzu-Wei Lin; Chang Liu 034; Shreepad Panth; et al. (ISSCC, 2012)

Design for pre-bond testability in 3D integrated circuits. - Dean L. Lewis (2012)

Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory). - Daehyun Kim 004; Krit Athikulwongse; Michael B. Healy; Mohammad M. Hossain; Moongon Jung; Ilya Khorosh; Gokul Kumar; Young-Joon Lee; Dean L. Lewis; Tzu-Wei Lin; Chang Liu 034; Shreepad Panth; et al. (IEEE Trans. Computers, 2015)