Timing analysis including clock skew. - David L. Harris; Mark Horowitz; Dean Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

A variable-frequency parallel I/O interface with adaptive power-supply regulation. - Gu-Yeon Wei; Jaeha Kim; Dean Liu; Stefanos Sidiropoulos; Mark A. Horowitz (IEEE J. Solid State Circuits, 2000)

IC Power Distribution Challenges. - Sudhakar Bobba; Tyler Thorp; Kathirgamar Aingaran; Dean Liu (ICCAD, 2001)

Macro-modeling concepts for the chip electrical interface. - Brian W. Amick; Claude R. Gauthier; Dean Liu (DAC, 2002)

Analysis of Blocking Dynamic Circuits. - Tyler Thorp; Dean Liu (ICCD, 2002)

Fast frequency acquisition phase-frequency detectors for Gsamples/s phase-locked loops. - Mozhgan Mansuri; Dean Liu; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2002)

A Framework for Designing Reusable Analog Circuits. - Dean Liu; Stefanos Sidiropoulos; Mark Horowitz (ICCAD, 2003)

Architecture and circuit techniques for a 1.1-GHz 16-kb reconfigurable memory in 0.18-μm CMOS. - Ken Mai; Ron Ho; Elad Alon; Dean Liu; Younggon Kim; Dinesh Patil; Mark A. Horowitz (IEEE J. Solid State Circuits, 2005)

An integrated VCSEL driver for 10Gb ethernet in 0.13µm CMOS. - Shahriar Rabii; Nikhil Acharya; Pak Chau; Joseph Dao; Arnold Feldman; Haw-Jyh Liaw; Dean Liu; Marc Loinaz; Manuel Luschas; Azmeer Salleh; Siddharth Sheth; Stefanos Sidiropoulos; et al. (ISSCC, 2006)

A 10.3GS/s 6b flash ADC for 10G Ethernet applications. - Shwetabh Verma; Athos Kasapi; Li-min Lee; Dean Liu; Dimitri Loizos; Song-Hee Paik; Aida Varzaghani; Sotirios Zogopoulos; Stefanos Sidiropoulos (ISSCC, 2013)

A 112Gb/s Serial Link Transceiver With 3-tap FFE and 18-tap DFE Receiver for up to 43dB Insertion Loss Channel in 7nm FinFET Technology. - Bo Zhang 029; Anand Vasani; Ashutosh Sinha; Alireza Nilchi; Haitao Tong; Lakshmi P. Rao; Karapet Khanoyan; Hamid Hatamkhani; Xiaochen Yang; Xin Meng; Alexander Wong; Jun Kim; et al. (ISSCC, 2023)

A 112-Gb/s Serial Link Transceiver With Three-Tap FFE and 18-Tap DFE Receiver for up to 43-dB Insertion Loss Channel in 7-nm FinFET Technology. - Bo Zhang 029; Anand Vasani; Ashutosh Sinha; Alireza Nilchi; Haitao Tong; Lakshmi P. Rao; Karapet Khanoyan; Hamid Hatamkhani; Xiaochen Yang; Xin Meng; Alexander Wong; Jun Kim; et al. (IEEE J. Solid State Circuits, 2024)