The IBM z13 processor cache subsystem. - Craig R. Walters; Pak-kin Mak; Deanna Postles Dunn Berger; Michael A. Blake; Tim Bronson; K. D. Klapproth; A. J. O'Neill; Robert J. Sonnelitter; Vesselina K. Papazova (IBM J. Res. Dev., 2015)

Design of the IBM z15 microprocessor. - Anthony Saporito; Martin Recktenwald; Christian Jacobi 002; Gerrit Koch; Deanna Postles Dunn Berger; Robert J. Sonnelitter; Craig R. Walters; Jang-Soo Lee; Cédric Lichtenau; Ulrich Mayer; Eduard Herkel; Stefan Payer; et al. (IBM J. Res. Dev., 2020)

Enterprise-Class Multilevel Cache Design: Low Latency, Huge Capacity, and High Reliability. - Deanna Postles Dunn Berger; Christian Jacobi 002; Craig R. Walters; Robert J. Sonnelitter; Mike Cadigan; Matthias Klein (IEEE Micro, 2023)

Enterprise-Class Cache Compression Design. - Alper Buyuktosunoglu; David Trilla; Bülent Abali; Deanna Postles Dunn Berger; Craig R. Walters; Jang-Soo Lee (HPCA, 2024)

Enterprise Class Modular Cache Hierarchy. - Craig R. Walters; Deanna Postles Dunn Berger; Robert J. Sonnelitter; Alper Buyuktosunoglu (HPCA, 2025)