A Novel Strategy to Test Core Based Designs. - Debabrata Bagchi; Dipanwita Roy Chowdhury; Joy Mukherjee; Santanu Chattopadhyay (VLSI Design, 2001)

PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations. - Alex K. Jones; Debabrata Bagchi; Satrajit Pal; Xiaoyong Tang; Alok N. Choudhary; Prithviraj Banerjee (CASES, 2002)

A Behavioral Synthesis Tool for Exploiting Fine Grain Parallelism in FPGAs. - Prithviraj Banerjee; Malay Haldar; Anshuman Nayak; Victor Kim; Debabrata Bagchi; Satrajit Pal; Nikhil Tripathi (IWDC, 2002)

Automatic Conversion of Floating Point MATLAB Programs into Fixed Point FPGA Based Hardware Design. - Prithviraj Banerjee; Debabrata Bagchi; Malay Haldar; Anshuman Nayak; Victor Kim; R. Uribe (FCCM, 2003)

Making area-performance tradeoffs at the high level using the AccelFPGA compiler for FPGAs. - Prithviraj Banerjee; Vikram Saxena; Juan Ramon Uribe; Malay Haldar; Anshuman Nayak; Victor Kim; Debabrata Bagchi; Satrajit Pal; Nikhil Tripathi; Robert Anderson (FPGA, 2003)

Overview of a compiler for synthesizing MATLAB programs onto FPGAs. - Prithviraj Banerjee; Malay Haldar; Anshuman Nayak; Victor Kim; Vikram Saxena; Steven Parkes; Debabrata Bagchi; Satrajit Pal; Nikhil Tripathi; David Zaretsky; Robert Anderson; Juan Ramon Uribe (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Leveraging UPF-extracted assertions for modeling and formal verification of architectural power intent. - Aritra Hazra; Srobona Mitra; Pallab Dasgupta; Ajit Pal; Debabrata Bagchi; Kaustav Guha (DAC, 2010)

Integrating Simulations to Increase Efficacy of the Teaching-Learning Process. - Debabrata Bagchi (T4E, 2011)