Low-power process-variation tolerant arithmetic units using input-based elastic clocking. - Debabrata Mohapatra; Georgios Karakonstantis; Kaushik Roy 001 (ISLPED, 2007)

A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors. - Ik Joon Chang; Debabrata Mohapatra; Kaushik Roy 001 (DAC, 2009)

Significance driven computation: a voltage-scalable, variation-aware, quality-tuning motion estimator. - Debabrata Mohapatra; Georgios Karakonstantis; Kaushik Roy 001 (ISLPED, 2009)

System level DSP synthesis using voltage overscaling, unequal error protection & adaptive quality tuning. - Georgios Karakonstantis; Debabrata Mohapatra; Kaushik Roy 001 (SiPS, 2009)

Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency. - Vinay K. Chippa; Debabrata Mohapatra; Anand Raghunathan; Kaushik Roy 001; Srimat T. Chakradhar (DAC, 2010)

VEDA: Variation-aware energy-efficient Discrete Wavelet Transform architecture. - Vaibhav Gupta; Georgios Karakonstantis; Debabrata Mohapatra; Kaushik Roy 001 (ICCD, 2010)

Voltage Scalable High-Speed Robust Hybrid Arithmetic Units Using Adaptive Clocking. - Swaroop Ghosh; Debabrata Mohapatra; Georgios Karakonstantis; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Variation-tolerant and self-repair design methodology for low temperature polycrystalline silicon liquid crystal and organic light emitting diode displays. - Chih-Hsiang Ho; Chao Lu 005; Debabrata Mohapatra; Kaushik Roy 001 (ASP-DAC, 2011)

Design of voltage-scalable meta-functions for approximate computing. - Debabrata Mohapatra; Vinay K. Chippa; Anand Raghunathan; Kaushik Roy 001 (DATE, 2011)

IMPACT: imprecise adders for low-power approximate computing. - Vaibhav Gupta; Debabrata Mohapatra; Sang Phill Park; Anand Raghunathan; Kaushik Roy 001 (ISLPED, 2011)

A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications. - Ik Joon Chang; Debabrata Mohapatra; Kaushik Roy 001 (IEEE Trans. Circuits Syst. Video Technol., 2011)

Empirical Evidence Against CAPM: Relating Alphas and Returns to Betas. - Mayur Agrawal; Debabrata Mohapatra; Ilya Pollak (IEEE J. Sel. Top. Signal Process., 2012)

Logic and Memory Design Based on Unequal Error Protection for Voltage-scalable, Robust and Adaptive DSP Systems. - Georgios Karakonstantis; Debabrata Mohapatra; Kaushik Roy 001 (J. Signal Process. Syst., 2012)

Energy-efficient recognition and mining processor using scalable effort design. - Vinay K. Chippa; Hrishikesh Jayakumar; Debabrata Mohapatra; Kaushik Roy 001; Anand Raghunathan (CICC, 2013)

How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core. - Moongon Jung; Taigon Song; Yang Wan; Young-Joon Lee; Debabrata Mohapatra; Hong Wang; Greg Taylor; Devang Jariwala; Vijay Pitchumani; Patrick Morrow; Clair Webb; Paul Fischer; et al. (CICC, 2013)

Low-Power Digital Signal Processing Using Approximate Adders. - Vaibhav Gupta; Debabrata Mohapatra; Anand Raghunathan; Kaushik Roy 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Scalable Effort Hardware Design. - Vinay Kumar Chippa; Debabrata Mohapatra; Kaushik Roy 001; Srimat T. Chakradhar; Anand Raghunathan (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Special Session: Approximate TinyML Systems: Full System Approximations for Extreme Energy-Efficiency in Intelligent Edge Devices. - Arnab Raha; Soumendu Kumar Ghosh; Debabrata Mohapatra; Deepak A. Mathaikutty; Raymond Sung; Cormac Brick; Vijay Raghunathan (ICCD, 2021)

Design Considerations for Edge Neural Network Accelerators: An Industry Perspective. - Arnab Raha; Sang Kyun Kim; Deepak Mathaikutty; Guruguhanathan Venkataramanan; Debabrata Mohapatra; Raymond Sung; Cormac Brick; Gautham N. Chinya (VLSID, 2021)

XRBench: An Extended Reality (XR) Machine Learning Benchmark Suite for the Metaverse. - Hyoukjun Kwon; Krishnakumar Nair; Jamin Seo; Jason Yik; Debabrata Mohapatra; Dongyuan Zhan; Jinook Song; Peter Capak; Peizhao Zhang; Peter Vajda; Colby R. Banbury; Mark Mazumder; et al. (MLSys, 2023)

A 3D Design Methodology for Integrated Wearable SoCs: Enabling Energy Efficiency and Enhanced Performance at Iso-Area Footprint. - Huseyin Ekin Sumbul; Arne Symons; Lita Yang; Huichu Liu; Tony F. Wu; Matheus Trevisan Moreira; Debabrata Mohapatra; Abhinav Agarwal; Kaushik Ravindran; Chris Thompson; Yuecheng Li; Edith Beigné (DATE, 2025)