Gm-cell nonlinearity compensation technique using single-bit quantiser and FIR DAC in Gm-C based delta-sigma modulators. - Debajit Basak; Kong-Pang Pun (ISCAS, 2016)

A 10-bit 2 MS/s SAR ADC using reverse VCM-based switching scheme. - Zhongyi Fu; Xian Tang; Daxiang Li 001; Jiangpeng Wang; Debajit Basak; Kong-Pang Pun (ISCAS, 2016)

Continuous-time delta-sigma modulator with an upfront passive-RC low-pass network. - Daxiang Li 001; Yang Zhang 034; Debajit Basak; Kong-Pang Pun (ISOCC, 2017)

An On-Chip Static and Dynamic DAC Error Correction Technique for High Speed Multibit Delta-Sigma Modulators. - Debajit Basak; Sarthak Kalani; Peter R. Kinget; Kong-Pang Pun (ISCAS, 2018)

A Gm-C Delta-Sigma Modulator With a Merged Input-Feedback Gm Circuit for Nonlinearity Cancellation and Power Efficiency Enhancement. - Debajit Basak; Daxiang Li 001; Kong-Pang Pun (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Improving Power Efficiency for Active-RC Delta-Sigma Modulators Using a Passive-RC Low-Pass Filter in the Feedback. - Daxiang Li 001; Debajit Basak; Yang Zhang 034; Zhongyi Fu; Kong-Pang Pun (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

An Automatic On-Chip Calibration Technique for Static and Dynamic DAC Error Correction in High-Speed Continuous-Time Delta-Sigma Modulators. - Debajit Basak; Sarthak Kalani; Yang Zhang 034; Kong-Pang Pun (IEEE Access, 2019)

A Highly Linear Multi-Level SC DAC in a Power-Efficient Gm-C Continuous-Time Delta-Sigma Modulator. - Yang Zhang 034; Debajit Basak; Kong-Pang Pun (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Power-Efficient Gm-C DSMs With High Immunity to Aliasing, Clock Jitter, and ISI. - Yang Zhang 034; Debajit Basak; Kong-Pang Pun (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A 0.59-mW 78.7-dB SNDR 2-MHz Bandwidth Active-RC Delta-Sigma Modulator With Relaxed and Reduced Amplifiers. - Hetong Wang; Debajit Basak; Yang Zhang 034; Kong-Pang Pun (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A Novel Current Comparator Enabling Large RRAM Crossbars for BNNs and PUFs. - Gokulnath Rajendran; Debajit Basak; Suman Deb; Siyi Wang; Anupam Chattopadhyay (VLSI-SoC, 2024)

An Efficient 1.4-GS/s 10-bit Timing-Skew-Free Time-Interleaved SAR ADC With a Centralized Sampling Frontend. - Siji Huang; Debajit Basak; Yanhang Chen; Qifeng Huang; Yifei Fan; Jie Yuan (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Securing Binarized Neural Networks via PUF-Based Key Management in Memristive Crossbar Arrays. - Gokulnath Rajendran; Debajit Basak; Suman Deb; Anupam Chattopadhyay (IEEE Embed. Syst. Lett., 2025)

On the Effect of Memory Error in a Time-Interleaved Pipeline ADC With a Shared Residue Amplifier. - Debajit Basak; Siji Huang; George Yuan (IEEE Trans. Circuits Syst. II Express Briefs, 2025)