Exhaustive and Near-Exhaustive Memory Testing Techniques and their BIST Implementations. - Debaleena Das; Mark G. Karpovsky (J. Electron. Test., 1997)

Fault diagnosis in scan-based BIST using both time and space information. - Jayabrata Ghosh-Dastidar; Debaleena Das; Nur A. Touba (ITC, 1999)

A Low Cost Approach for Detecting, Locating, and Avoiding Interconnect Faults in FPGA-Based Reconfigurable Systems. - Debaleena Das; Nur A. Touba (VLSI Design, 1999)

Weight-Based Codes and Their Application to Concurrent Error Detection of Multilevel Circuits. - Debaleena Das; Nur A. Touba (VTS, 1999)

Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes. - Debaleena Das; Nur A. Touba (J. Electron. Test., 1999)

Low Cost Concurrent Error Detection Based on Modulo Weight-Based Codes. - Debaleena Das; Nur A. Touba; Markus Seuring; Michael Gössel (IOLTW, 2000)

Reducing test data volume using external/LBIST hybrid test patterns. - Debaleena Das; Nur A. Touba (ITC, 2000)