Power Reduction by Integrated Within_Clock_Power Gating and Power Gating (WCPG_in_PG). - Debanjali Nath; Priyanka Choudhury; Sambhu Nath Pradhan (VDAT, 2013)

Power gating architecture implementation inside clock period to reduce power. - Debanjali Nath; Priyanka Choudhury; Abhishek Nag; Sambhu Nath Pradhan (Int. J. Comput. Aided Eng. Technol., 2014)

Thermal aware AND-OR-XOR network synthesis. - Priyanka Choudhury; Debanjali Nath; Vivek Rai; Sambhu Nath Pradhan (VDAT, 2015)

Layout-oriented look up table-based dual threshold approach to reduce leakage. - Sambhu Nath Pradhan; Angshuman Chakraborty; Abhishek Nag; Debanjali Nath (Int. J. Comput. Aided Eng. Technol., 2015)

Hybrid Approach of Within-Clock Power Gating and Normal Power Gating to Reduce Power. - Debanjali Nath; Priyanka Choudhury; Sambhu Nath Pradhan (J. Circuits Syst. Comput., 2016)

Transistor level realisation of power gated FSM. - Sambhu Nath Pradhan; Priyanka Choudhury; Debanjali Nath (Int. J. Comput. Aided Eng. Technol., 2017)

Leakage Reduction of SRAM-Based Look-Up Table Using Dynamic Power Gating. - Abhishek Nag; Debanjali Nath; Sambhu Nath Pradhan (J. Circuits Syst. Comput., 2017)

FPGA and ASIC realisation of EMD algorithm for real-time signal processing. - Kaushik Das; Debanjali Nath; Sambhu Nath Pradhan (IET Circuits Devices Syst., 2020)