An Efficient High Speed Implementation of Flexible Characteristic-2 Multipliers on FPGAs. - Debapriya Basu Roy; Debdeep Mukhopadhyay (VDAT, 2012)

Role of power grid in side channel attack and power-grid-aware secure design. - Xinmu Wang; Wen Yueh; Debapriya Basu Roy; Seetharam Narasimhan; Yu Zheng 011; Saibal Mukhopadhyay; Debdeep Mukhopadhyay; Swarup Bhunia (DAC, 2013)

Tile Before Multiplication: An Efficient Strategy to Optimize DSP Multiplier for Accelerating Prime Field ECC for NIST Curves. - Debapriya Basu Roy; Debdeep Mukhopadhyay; Masami Izumi; Junko Takahashi (DAC, 2014)

Integrated Sensor: A Backdoor for Hardware Trojan Insertions? - Xuan Thuy Ngo; Zakaria Najm; Shivam Bhasin; Debapriya Basu Roy; Jean-Luc Danger; Sylvain Guilley (DSD, 2015)

From theory to practice of private circuit: A cautionary note. - Debapriya Basu Roy; Shivam Bhasin; Sylvain Guilley; Jean-Luc Danger; Debdeep Mukhopadhyay (ICCD, 2015)

Reconfigurable LUT: A Double Edged Sword for Security-Critical Applications. - Debapriya Basu Roy; Shivam Bhasin; Sylvain Guilley; Jean-Luc Danger; Debdeep Mukhopadhyay; Xuan Thuy Ngo; Zakaria Najm (SPACE, 2015)

Exploiting the Order of Multiplier Operands: A Low Cost Approach for HCCA Resistance. - Poulami Das 003; Debapriya Basu Roy; Debdeep Mukhopadhyay (IACR Cryptol. ePrint Arch., 2015)

Using Tweaks To Design Fault Resistant Ciphers. - Sikhar Patranabis; Debapriya Basu Roy; Debdeep Mukhopadhyay (IACR Cryptol. ePrint Arch., 2015)

ECC on Your Fingertips: A Single Instruction Approach for Lightweight ECC Design in GF (p). - Debapriya Basu Roy; Poulami Das 003; Debdeep Mukhopadhyay (IACR Cryptol. ePrint Arch., 2015)

Reconfigurable LUT: Boon or Bane for Secure Applications. - Debapriya Basu Roy; Shivam Bhasin; Sylvain Guilley; Jean-Luc Danger; Debdeep Mukhopadhyay (IACR Cryptol. ePrint Arch., 2015)

Improved Atomicity to Prevent HCCA on NIST Curves. - Poulami Das 003; Debapriya Basu Roy; Debdeep Mukhopadhyay (AsiaPKC@AsiaCCS, 2016)

Inner collisions in ECC: Vulnerabilities of complete addition formulas for NIST curves. - Poulami Das 003; Debapriya Basu Roy; Harishma Boyapally; Debdeep Mukhopadhyay (AsianHOST, 2016)

Parsimonious design strategy for linear layers with high diffusion in block ciphers. - Sikhar Patranabis; Debapriya Basu Roy; Yash Shrivastava; Debdeep Mukhopadhyay; Santosh Ghosh (HOST, 2016)

Shuffling across rounds: A lightweight strategy to counter side-channel attacks. - Sikhar Patranabis; Debapriya Basu Roy; Praveen Kumar Vadnala; Debdeep Mukhopadhyay; Santosh Ghosh (ICCD, 2016)

Accelerating OpenSSL's ECC with low cost reconfigurable hardware. - Debapriya Basu Roy; Shubham Agrawal; Chester Rebeiro; Debdeep Mukhopadhyay (ISIC, 2016)

SmashClean: A hardware level mitigation to stack smashing attacks in OpenRISC. - Manaar Alam; Debapriya Basu Roy; Sarani Bhattacharya; Vidya Govindan; Rajat Subhra Chakraborty; Debdeep Mukhopadhyay (MEMOCODE, 2016)

Secure public key hardware for IoT applications. - Poulami Das 003; Debapriya Basu Roy; Debdeep Mukhopadhyay (MWSCAS, 2016)

Fault Based Almost Universal Forgeries on CLOC and SILC. - Debapriya Basu Roy; Avik Chakraborti; Donghoon Chang; S. V. Dilip Kumar; Debdeep Mukhopadhyay; Mridul Nandi (SPACE, 2016)

Exploiting Safe Error based Leakage of RFID Authentication Protocol using Hardware Trojan Horse. - Krishna Bagadia; Urbi Chatterjee; Debapriya Basu Roy; Debdeep Mukhopadhyay; Rajat Subhra Chakraborty (IACR Cryptol. ePrint Arch., 2016)

What Lies Ahead: Extending TVLA Testing Methodology Towards Success Rate. - Debapriya Basu Roy; Shivam Bhasin; Sikhar Patranabis; Debdeep Mukhopadhyay; Sylvain Guilley (IACR Cryptol. ePrint Arch., 2016)

Side-Channel Watchdog: Run-Time Evaluation of Side-Channel Vulnerability in FPGA-Based Crypto-systems. - Souvik Sonar; Debapriya Basu Roy; Rajat Subhra Chakraborty; Debdeep Mukhopadhyay (IACR Cryptol. ePrint Arch., 2016)

Using Tweaks To Design Fault Resistant Ciphers (Full Version). - Sikhar Patranabis; Debapriya Basu Roy; Debdeep Mukhopadhyay (Conf. Computing Frontiers, 2017)

Side Channel Evaluation of PUF-Based Pseudorandom Permutation. - Durga Prasad Sahoo; Phuong Ha Nguyen; Debapriya Basu Roy; Debdeep Mukhopadhyay; Rajat Subhra Chakraborty (DSD, 2017)

Opening pandora's box: Implication of RLUT on secure FPGA applications and IP security. - Debapriya Basu Roy; Shivam Bhasin; Ivica Nikolic; Debdeep Mukhopadhyay (IVSW, 2017)

Two Efficient Fault-Based Attacks on CLOC and SILC. - Debapriya Basu Roy; Avik Chakraborti; Donghoon Chang; S. V. Dilip Kumar; Debdeep Mukhopadhyay; Mridul Nandi (J. Hardw. Syst. Secur., 2017)

Revisiting FPGA Implementation of Montgomery Multiplier in Redundant Number System for Efficient ECC Application in GF(p). - Debdeep Mukhopadhyay; Debapriya Basu Roy (FPL, 2018)

Minimalistic Perspective to Public Key Implementations on FPGA. - Debapriya Basu Roy; Debdeep Mukhopadhyay (ISVLSI, 2018)

Customized Instructions for Protection Against Memory Integrity Attacks. - Debapriya Basu Roy; Manaar Alam; Sarani Bhattacharya; Vidya Govindan; Francesco Regazzoni 001; Rajat Subhra Chakraborty; Debdeep Mukhopadhyay (IEEE Embed. Syst. Lett., 2018)

The Conflicted Usage of RLUTs for Security-Critical Applications on FPGA. - Debapriya Basu Roy; Shivam Bhasin; Jean-Luc Danger; Sylvain Guilley; Wei He 015; Debdeep Mukhopadhyay; Zakaria Najm; Xuan Thuy Ngo (J. Hardw. Syst. Secur., 2018)

Number "Not Used" Once - Practical Fault Attack on pqm4 Implementations of NIST Candidates. - Prasanna Ravi; Debapriya Basu Roy; Shivam Bhasin; Anupam Chattopadhyay; Debdeep Mukhopadhyay (COSADE, 2019)

Revisiting the Security of LPN Based RFID Authentication Protocol and Potential Exploits in Hardware Implementations. - Krishna Bagadia; Urbi Chatterjee; Debapriya Basu Roy; Debdeep Mukhopadhyay; Rajat Subhra Chakraborty (SPACE, 2019)

Enhancing Fault Tolerance of Neural Networks for Security-Critical Applications. - Manaar Alam; Arnab Bag; Debapriya Basu Roy; Dirmanto Jap; Jakub Breier; Shivam Bhasin; Debdeep Mukhopadhyay (CoRR, 2019)

Count Your Toggles: a New Leakage Model for Pre-Silicon Power Analysis of Crypto Designs. - Rajat Sadhukhan; Paulson Mathew; Debapriya Basu Roy; Debdeep Mukhopadhyay (J. Electron. Test., 2019)

Post Quantum ECC on FPGA Platform. - Debapriya Basu Roy; Debdeep Mukhopadhyay (IACR Cryptol. ePrint Arch., 2019)

Breach the Gate: Exploiting Observability for Fault Template Attacks on Block Ciphers. - Sayandeep Saha; Debapriya Basu Roy; Arnab Bag; Sikhar Patranabis; Debdeep Mukhopadhyay (IACR Cryptol. ePrint Arch., 2019)

Automatic generation of HCCA-resistant scalar multiplication algorithm by proper sequencing of field multiplier operands. - Poulami Das 003; Debapriya Basu Roy; Debdeep Mukhopadhyay (J. Cryptogr. Eng., 2019)

Lightweight Design-for-Security Strategies for Combined Countermeasures Against Side Channel and Fault Analysis in IoT Applications. - Sikhar Patranabis; Debapriya Basu Roy; Anirban Chakraborty 003; Naveen Nagar; Astikey Singh; Debdeep Mukhopadhyay; Santosh Ghosh (J. Hardw. Syst. Secur., 2019)

CC Meets FIPS: A Hybrid Test Methodology for First Order Side Channel Analysis. - Debapriya Basu Roy; Shivam Bhasin; Sylvain Guilley; Annelie Heuser; Sikhar Patranabis; Debdeep Mukhopadhyay (IEEE Trans. Computers, 2019)

Combining PUF with RLUTs: A Two-party Pay-per-device IP Licensing Scheme on FPGAs. - Debapriya Basu Roy; Shivam Bhasin; Ivica Nikolic; Debdeep Mukhopadhyay (ACM Trans. Embed. Comput. Syst., 2019)

High-Speed Implementation of ECC Scalar Multiplication in GF(p) for Generic Montgomery Curves. - Debapriya Basu Roy; Debdeep Mukhopadhyay (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Fault Template Attacks on Block Ciphers Exploiting Fault Propagation. - Sayandeep Saha; Arnab Bag; Debapriya Basu Roy; Sikhar Patranabis; Debdeep Mukhopadhyay (EUROCRYPT (1), 2020)

Efficient Hardware/Software Co-Design for Post-Quantum Crypto Algorithm SIKE on ARM and RISC-V based Microcontrollers. - Debapriya Basu Roy; Tim Fritzmann; Georg Sigl (ICCAD, 2020)

Cryptographically Secure Multi-tenant Provisioning of FPGAs. - Arnab Bag; Sikhar Patranabis; Debapriya Basu Roy; Debdeep Mukhopadhyay (SPACE, 2020)

A Minimalistic Perspective on Koblitz Curve Scalar Multiplication for FPGA Platforms. - Siddhartha Chowdhury; Debapriya Basu Roy; Debdeep Mukhopadhyay (VLSI-SOC, 2020)

Neural Network-based Inherently Fault-tolerant Hardware Cryptographic Primitives without Explicit Redundancy Checks. - Manaar Alam; Arnab Bag; Debapriya Basu Roy; Dirmanto Jap; Jakub Breier; Shivam Bhasin; Debdeep Mukhopadhyay (ACM J. Emerg. Technol. Comput. Syst., 2020)

A Framework to Counter Statistical Ineffective Fault Analysis of Block Ciphers Using Domain Transformation and Error Correction. - Sayandeep Saha; Dirmanto Jap; Debapriya Basu Roy; Avik Chakraborty; Shivam Bhasin; Debdeep Mukhopadhyay (IEEE Trans. Inf. Forensics Secur., 2020)

Efficient Loop Abort Fault Attacks on Supersingular Isogeny based Key Exchange (SIKE). - Piyush Beegala; Debapriya Basu Roy; Prasanna Ravi; Shivam Bhasin; Anupam Chattopadhyay; Debdeep Mukhopadhyay (DFT, 2022)

FlexiPair: An Automated Programmable Framework for Pairing Cryptosystems. - Arnab Bag; Debapriya Basu Roy; Sikhar Patranabis; Debdeep Mukhopadhyay (IEEE Trans. Computers, 2022)

Multiplierless Design of Very Large Constant Multiplications in Cryptography. - Levent Aksoy; Debapriya Basu Roy; Malik Imran; Patrick Karl; Samuel Pagliarini (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Masked Accelerators and Instruction Set Extensions for Post-Quantum Cryptography. - Tim Fritzmann; Michiel Van Beirendonck; Debapriya Basu Roy; Patrick Karl; Thomas Schamberger; Ingrid Verbauwhede; Georg Sigl (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022)

A Comparative Analysis between Karatsuba, Toom-Cook and NTT Multiplier for Polynomial Multiplication in NTRU on FPGA. - Harish Prasad Allam; Suraj Mandal; Debapriya Basu Roy (AsianHOST, 2023)

Multiplierless Design of High-Speed Very Large Constant Multiplications. - Levent Aksoy; Debapriya Basu Roy; Malik Imran; Samuel Pagliarini (ASPDAC, 2024)

Automatic Generation of Modular Multipliers Upon Pseudo-Mersenne Primes Using DSP Blocks on FPGAs. - Shree Harish S; Debapriya Basu Roy (DSD, 2024)

Design of a Lightweight Fast Fourier Transformation for FALCON using Hardware-Software Co-Design. - Suraj Mandal; Debapriya Basu Roy (ACM Great Lakes Symposium on VLSI, 2024)

KiD: A Hardware Design Framework Targeting Unified NTT Multiplication for CRYSTALS-Kyber and CRYSTALS-Dilithium on FPGA. - Suraj Mandal; Debapriya Basu Roy (VLSID, 2024)

Hardware Circuits and Systems Design for Post-Quantum Cryptography - A Tutorial Brief. - Jiafeng Xie; Wenfeng Zhao; Hanho Lee; Debapriya Basu Roy; Xinmiao Zhang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Uniform instruction set extensions for multiplications in contemporary and post-quantum cryptography. - Felix Oberhansl; Tim Fritzmann; Thomas Pöppelmann; Debapriya Basu Roy; Georg Sigl (J. Cryptogr. Eng., 2024)

Winograd for NTT: A Case Study on Higher-Radix and Low-Latency Implementation of NTT for Post Quantum Cryptography on FPGA. - Suraj Mandal; Debapriya Basu Roy (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Three Eyed Raven: An On-Chip Side Channel Analysis Framework for Run-Time Evaluation. - M. Dhilipkumar; Priyanka Bagade; Debapriya Basu Roy (DATE, 2025)