Hierarchical modeling and test generation for digital circuits. - Debashis Bhattacharya (1988)

High-Level Test Generation for VLSI. - Debashis Bhattacharya; Brian T. Murray; John P. Hayes (Computer, 1989)

Binary to Quaternary Encoding in Clocked CMOS Circuits Using Weak Buffer. - Debashis Bhattacharya (ISMVL, 1990)

CMP3F: a high speed fault simulator for the Connection Machine. - Ajit Agrawal; Debashis Bhattacharya (ITC, 1990)

A hierarchical test generation methodology for digital circuits. - Debashis Bhattacharya; John P. Hayes (J. Electron. Test., 1990)

Designing for high-level test generation. - Debashis Bhattacharya; John P. Hayes (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

TSUNAMI: A Path Oriented Scheme for Algebraic Test Generation. - Ted Stanion; Debashis Bhattacharya (FTCS, 1991)

Delay Fault Test Generation for Scan/Hold Circuits Using Boolean Expressions. - Debashis Bhattacharya; Prathima Agrawal; Vishwani D. Agrawal (DAC, 1992)

Boolean algebraic test generation using a distributed system. - Debashis Bhattacharya; Prathima Agrawal (ICCAD, 1993)

Pipelined Fault Simulation on Parallel Machines Using the Circuit Flow Graph. - Shang-E Tai; Debashis Bhattacharya (ICCD, 1993)

Architecture of a Min-Max Simulator on MARS. - Kumar N. Lalgudi; Debashis Bhattacharya; Prathima Agrawal (VLSI Design, 1993)

A Three-Stage Partial Scan Design Method Using the Sequential Circuit Flow Graph. - Shang-E Tai; Debashis Bhattacharya (VLSI Design, 1994)

A three-stage partial scan design method to ease ATPG. - Shang-E Tai; Debashis Bhattacharya (J. Electron. Test., 1995)

Test Generation for Path Delay Faults Using Binary Decision Diagrams. - Debashis Bhattacharya; Prathima Agrawal; Vishwani D. Agrawal (IEEE Trans. Computers, 1995)

An efficient method for generating exhaustive test sets. - Ted Stanion; Debashis Bhattacharya; Carl Sechen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Optimizing computations in a transposed direct form realization of floating-point LTI-FIR systems. - Naushik Sankarayya; Kaushik Roy 001; Debashis Bhattacharya (ICCAD, 1997)

Optimizing Test Hardware for At-Speed Testing of Datapaths in an Integrated Circuit. - Debashis Bhattacharya; Smith Freeman; Bill Lin 002 (VLSI Design, 1997)

Algorithms for Low Power FIR Filter Realization Using Differential Coefficients. - Naushik Sankarayya; Kaushik Roy 001; Debashis Bhattacharya (VLSI Design, 1997)

Invariance of stereo images via the theory of complex moments. - Debashis Bhattacharya; Satyabroto Sinha (Pattern Recognit., 1997)

Hierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit. - Debashis Bhattacharya (VTS, 1998)

Instruction-Driven Wake-Up Mechanisms for Snoopy TAP Controller. - Debashis Bhattacharya (VTS, 1999)

Transistor-Level Optimization of Digital Designs with Flex Cells. - Rob Roy; Debashis Bhattacharya; Vamsi Boppana (Computer, 2005)