A Model of Spurs for Delta-Sigma Fractional PLLs. - Debdut Biswas; Tarun Kanti Bhattacharyya (VLSID, 2019)

Spur reduction architecture for multiphase fractional PLLs. - Debdut Biswas; Tarun Kanti Bhattacharyya (IET Circuits Devices Syst., 2019)

Spur Reduction Circuit for Fractional-N PLLs. - Debdut Biswas (Circuits Syst. Signal Process., 2022)

A reference sampling ΔΣ subsampling PLL. - Debdut Biswas (Integr., 2024)