A Novel Approach for Subcube Allocation in Hypercube Multiprocessors. - Debendra Das Sharma; Dhiraj K. Pradhan (SPDP, 1992)

Roll-Forward Checkpointing Schemes. - Dhiraj K. Pradhan; Debendra Das Sharma; Nitin H. Vaidya (Hardware and Software Architectures for Fault Tolerance, 1993)

Fast and Efficient Strategies for Cubic and Non-Cubic Allocation in Hypercube Multiprocessors. - Debendra Das Sharma; Dhiraj K. Pradhan (ICPP (1), 1993)

A Fast and Efficient Strategy for Submesh Allocation in Mesh-Connected Parallel Computers. - Debendra Das Sharma; Dhiraj K. Pradhan (SPDP, 1993)

Subcube Level Time-Sharing in Hypercube Multicomputers. - Debendra Das Sharma; G. D. Holland; Dhiraj K. Pradhan (ICPP (2), 1994)

Job Scheduling in Mesh Multicomputers. - Debendra Das Sharma; Dhiraj K. Pradhan (ICPP (2), 1994)

Processor Allocation in Hypercube Multicomputers: Fast and Efficient Strategies for Cubic and Noncubic Allocation. - Debendra Das Sharma; Dhiraj K. Pradhan (IEEE Trans. Parallel Distributed Syst., 1995)

Submesh Allocation in Mesh Multicomputers Using Busy-List: A BestFit Approach with Complete Recognition Capability. - Debendra Das Sharma; Dhiraj K. Pradhan (J. Parallel Distributed Comput., 1996)

Intel® 5520 chipset: An I / O hub chipset for server, workstation, and high end desktop. - Debendra Das Sharma (Hot Chips Symposium, 2009)

PCI Express® 6.0 Specification at 64.0 GT/s with PAM-4 signaling: a low latency, high bandwidth, high reliability and cost-effective interconnect. - Debendra Das Sharma (Hot Interconnects, 2020)

Keynote 1: Compute Express Link (CXL) changing the game for Cloud Computing. - Debendra Das Sharma (HOTI, 2021)

A low latency approach to delivering alternate protocols with coherency and memory semantics using PCI Express® 6.0 PHY at 64.0 GT/s. - Debendra Das Sharma (HOTI, 2021)

PCI Express 6.0 Specification: A Low-Latency, High-Bandwidth, High-Reliability, and Cost-Effective Interconnect With 64.0 GT/s PAM-4 Signaling. - Debendra Das Sharma (IEEE Micro, 2021)

Compute Express Link®: An open industry-standard interconnect enabling heterogeneous data-centric computing. - Debendra Das Sharma (HOTI, 2022)

A Low-Latency and Low-Power Approach for Coherency and Memory Protocols on PCI Express 6.0 PHY at 64.0 GT/s With PAM-4 Signaling. - Debendra Das Sharma (IEEE Micro, 2022)

Invited: Compute Express Link™ (CXL™): An Open Interconnect for Cloud Infrastructure. - Debendra Das Sharma (DAC, 2023)

Pipelined and Partitionable Forward Error Correction and Cyclic Redundancy Check Circuitry Implementation for PCI Express® 6.0. - Debendra Das Sharma; Swadesh Choudhary (HOTI, 2023)

Novel Composable and Scaleout Architectures Using Compute Express Link. - Debendra Das Sharma (IEEE Micro, 2023)

System on a Package Innovations With Universal Chiplet Interconnect Express (UCIe) Interconnect. - Debendra Das Sharma (IEEE Micro, 2023)

Compute Express Link (CXL): Enabling Heterogeneous Data-Centric Computing With Heterogeneous Memory Hierarchy. - Debendra Das Sharma (IEEE Micro, 2023)

Pipelined and Partitionable Forward Error Correction and Cyclic Redundancy Check Circuitry Implementation for PCI Express 6.0 and Compute Express Link 3.0. - Debendra Das Sharma; Swadesh Choudhary (IEEE Micro, 2024)

Universal Chiplet Interconnect Express: An Open Industry Standard for Memory and Storage Applications. - Debendra Das Sharma; Thomas M. Coughlin (Computer, 2024)

An Introduction to the Compute Express Link (CXL) Interconnect. - Debendra Das Sharma; Robert Blankenship; Daniel S. Berger (ACM Comput. Surv., 2024)

Special Issue on Interconnects for Chiplet Integration Technologies. - Debendra Das Sharma; Nam Sung Kim (IEEE Micro, 2025)

On-Package Memory with Universal Chiplet Interconnect Express (UCIe): A Low Power, High Bandwidth, Low Latency and Low Cost Approach. - Debendra Das Sharma; Swadesh Choudhary; Peter Z. Onufryk; Rob Pelt (CoRR, 2025)