Logical redundancies in irredundant combinational circuits. - Susanta Chakraborty; Debesh Kumar Das; Bhargab B. Bhattacharya (J. Electron. Test., 1993)

Testable design of non-scan sequential circuits using extra logic. - Debesh K. Das; Bhargab B. Bhattacharya (Asian Test Symposium, 1995)

Does retiming affect redundancy in sequential circuits? - Debesh Kumar Das; Bhargab B. Bhattacharya (VLSI Design, 1996)

New BIST Techniques for Universal and Robust Testing of CMOS Stuck-Open Faults. - Debesh Kumar Das; Susanta Chakraborty; Bhargab B. Bhattacharya (VLSI Design, 1997)

Interchangeable Boolean Functions and Their Effects on Redundancy in Logic Circuits. - Debesh K. Das; Susanta Chakraborty; Bhargab B. Bhattacharya (ASP-DAC, 1998)

Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults. - Debesh K. Das; Indrajit Chaudhuri; Bhargab B. Bhattacharya (VLSI Design, 1998)

An Adaptive BIST to Detect Multiple Stuck-Open Faults in CMOS circuits. - Hafizur Rahaman 001; Debesh K. Das; Bhargab B. Bhattacharya (ASP-DAC, 1999)

New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency. - Debesh Kumar Das; Satoshi Ohtake; Hideo Fujiwara (Asian Test Symposium, 1999)

Synthesis of Symmetric Functions for Path-Delay Fault Testability. - Susanta Chakraborty; Sandip Das 001; Debesh K. Das; Bhargab B. Bhattacharya (VLSI Design, 1999)

Test Generation for Acyclic Sequential Circuits with Hold Registers. - Tomoo Inoue; Debesh Kumar Das; Chiiho Sano; Takahiro Mihara; Hideo Fujiwara (ICCAD, 2000)

Isomorph-Redundancy in Sequential Circuits. - Debesh K. Das; Uttam K. Bhattacharya; Bhargab B. Bhattacharya (IEEE Trans. Computers, 2000)

Synthesis of symmetric functions for path-delay fault testability. - Susanta Chakrabarti; Sandip Das 001; Debesh Kumar Das; Bhargab B. Bhattacharya (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Cellular automata as a built in self test structure. - Biplab K. Sikdar; Debesh K. Das; Vamsi Boppana; Cliff Yang; Sobhan Mukherjee; Parimal Pal Chaudhuri (ASP-DAC, 2001)

Enhancing BIST Quality of Sequential Machines through Degree-of-Freedom Analysis. - Biplab K. Sikdar; Samir Roy; Debesh K. Das (Asian Test Symposium, 2001)

Testable Design of Sequential Circuits with Improved Fault Efficiency. - Debesh Kumar Das; Bhargab B. Bhattacharya; Satoshi Ohtake; Hideo Fujiwara (VLSI Design, 2001)

Hierarchical Cellular Automata As An On-Chip Test Pattern Generator. - Biplab K. Sikdar; Purnabha Majumder; Monalisa Mukherjee; Parimal Pal Chaudhuri; Debesh K. Das; Niloy Ganguly (VLSI Design, 2001)

A New Synthesis of Symmetric Functions. - Hafizur Rahaman 001; Debesh K. Das; Bhargab B. Bhattacharya (ASP-DAC/VLSI Design, 2002)

Degree-of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area. - Samir Roy; Biplab K. Sikdar; Monalisa Mukherjee; Debesh K. Das (ASP-DAC/VLSI Design, 2002)

BIST Design for Detecting Multiple Stuck-Open Faults in CMOS Circuits Using Transition Count. - Hafizur Rahaman 001; Debesh K. Das; Bhargab B. Bhattacharya (J. Comput. Sci. Technol., 2002)

Mapping Symmetric Functions to Hierarchical Modules for Path-Delay Fault Testability. - Hafizur Rahaman 001; Debesh K. Das; Bhargab B. Bhattacharya (Asian Test Symposium, 2003)

A Simple Delay Testable Synthesis of Symmetric Functions. - Hafizur Rahaman 001; Debesh K. Das (AACC, 2004)

Testable design of GRM network with EXOR-tree for detecting stuck-at and bridging faults. - Hafizur Rahaman 001; Debesh K. Das; Bhargab B. Bhattacharya (ASP-DAC, 2004)

Max-Testable Class of Sequential Circuits having Combinational Test Generation Complexity. - Debesh Kumar Das; Tomoo Inoue; Susanta Chakraborty; Hideo Fujiwara (Asian Test Symposium, 2004)

Easily Testable Realization of GRM and ESOP Networks for Detecting Stuck-at and Bridging Faults. - Hafizur Rahaman 001; Debesh K. Das; Bhargab B. Bhattacharya (VLSI Design, 2004)

Design & Test Education in Asia. - Debesh K. Das; Hideo Fujiwara; Yungang Li; Yinghua Min; Shiyi Xu; Yervant Zorian (IEEE Des. Test Comput., 2004)

New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency. - Debesh Kumar Das; Satoshi Ohtake; Hideo Fujiwara (J. Electron. Test., 2004)

Bridging fault detection in Double Fixed-Polarity Reed-Muller (DFPRM) PLA. - Hafizur Rahaman 001; Debesh K. Das (ASP-DAC, 2005)

Synthesis of Testable Finite State Machine Through Decomposition. - Biplab K. Sikdar; Arijit Sarkar; Samir Roy; Debesh K. Das (Asian Test Symposium, 2005)

Cellular Automata Based Test Structures with Logic Folding. - Biplab K. Sikdar; Sukanta Das; Samir Roy; Niloy Ganguly; Debesh K. Das (VLSI Design, 2005)

A Degree-of-Freedom Based Synthesis Scheme for Sequential Machines with Enhanced BIST Quality and Reduced Area. - Biplab K. Sikdar; Samir Roy; Debesh K. Das (J. Electron. Test., 2005)

Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability. - Hafizur Rahaman 001; Debesh K. Das; Bhargab B. Bhattacharya (J. Electron. Test., 2006)

Optimum Test Set for Bridging Fault Detection in Reversible Circuits. - Hafizur Rahaman 001; Dipak Kumar Kole; Debesh K. Das; Bhargab B. Bhattacharya (ATS, 2007)

Key Note Speaker. - Debesh K. Das (ICIIS, 2008)

On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set. - Hafizur Rahaman 001; Dipak Kumar Kole; Debesh Kumar Das; Bhargab B. Bhattacharya (VLSI Design, 2008)

An Adaptive BIST Design for Detecting Multiple Stuck-Open Faults in a CMOS Complex Cell. - Hafizur Rahaman 001; Debesh K. Das; Bhargab B. Bhattacharya (IEEE Trans. Instrum. Meas., 2008)

Testable design of AND-EXOR logic networks with universal test sets. - Hafizur Rahaman 001; Debesh K. Das; Bhargab B. Bhattacharya (Comput. Electr. Eng., 2009)

Derivation of Optimal Test Set for Detection of Multiple Missing-Gate Faults in Reversible Circuits. - Dipak Kumar Kole; Hafizur Rahaman 001; Debesh K. Das; Bhargab B. Bhattacharya (Asian Test Symposium, 2010)

Derivation of Automatic Test Set for Detection of Missing Gate Faults in Reversible Circuits. - Dipak Kumar Kole; Hafizur Rahaman 001; Debesh K. Das; Bhargab B. Bhattacharya (ISED, 2011)

Optimizing Test Architecture for TSV Based 3D Stacked ICs Using Hard SOCs. - Surajit Kumar Roy; Chandan Giri; Arnab Chakraborty; Subhro Mukherjee; Debesh K. Das; Hafizur Rahaman 001 (ISED, 2011)

Fault diagnosis in reversible circuits under missing-gate fault model. - Hafizur Rahaman 001; Dipak Kumar Kole; Debesh K. Das; Bhargab B. Bhattacharya (Comput. Electr. Eng., 2011)

Reversible Logic Circuit Synthesis Using Genetic Algorithm and Particle Swarm Optimization. - Papia Manna; Dipak Kumar Kole; Hafizur Rahaman 001; Debesh K. Das; Bhargab B. Bhattacharya (ISED, 2012)

Optimal stacking of SOCs in a 3D-SIC for post-bond testing. - Manjari Pradhan; Chandan Giri; Hafizur Rahaman 001; Debesh K. Das (3DIC, 2013)

A design for testability technique for quantum reversible circuits. - Joyati Mondal; Debesh K. Das; Dipak Kumar Kole; Hafizur Rahaman 001 (EWDTS, 2013)

Reversible synthesis of symmetric boolean functions based on unate decomposition. - Arighna Deb; Debesh K. Das; Hafizur Rahaman 001; Bhargab B. Bhattacharya (ACM Great Lakes Symposium on VLSI, 2013)

The Design of Reversible Multiplier Using Ancient Indian Mathematics. - Arindam Banerjee 003; Debesh Kumar Das (ISED, 2013)

Modular Design for Symmetric Functions Using Quantum Quaternary Logic. - Arighna Deb; Debesh K. Das; Susmita Sur-Kolay (ISED, 2013)

Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure. - Arighna Deb; Debesh K. Das; Hafizur Rahaman 001; Bhargab B. Bhattacharya; Robert Wille; Rolf Drechsler (RC, 2013)

On Designing Testable Reversible Circuits Using Gate Duplication. - Joyati Mondal; Debesh Kumar Das; Dipak Kumar Kole; Hafizur Rahaman 001; Bhargab B. Bhattacharya (VDAT, 2013)

Derivation of test set for detecting multiple missing-gate faults in reversible circuits. - Dipak Kumar Kole; Hafizur Rahaman 001; Debesh K. Das; Bhargab B. Bhattacharya (Comput. Electr. Eng., 2013)

Generator for Test Set Construction of SMGF in Reversible Circuit by Boolean Difference Method. - Bappaditya Mondal; Dipak Kumar Kole; Debesh Kumar Das; Hafizur Rahaman 001 (ATS, 2014)

Squaring in reversible logic using iterative structure. - Arindam Banerjee 003; Debesh Kumar Das (EWDTS, 2014)

Optimizing test time for core-based 3-d integrated circuits by a technique of bi-partitioning. - Manjari Pradhan; Debesh K. Das; Chandan Giri; Hafizur Rahaman 001 (EWDTS, 2014)

Synthesis of Symmetric Boolean Functions Using a Three-Stage Network. - Arighna Deb; Debesh K. Das; Bhargab B. Bhattacharya (ISED, 2014)

Inadmissible Class of Boolean Functions under Stuck-at Faults. - Debesh K. Das; Debabani Chowdhury; Bhargab B. Bhattacharya; Tsutomu Sasao (ISMVL, 2014)

On Designing Robust Path-Delay Fault Testable Combinational Circuits Based on Functional Properties. - Rupali Mitra; Debesh K. Das; Bhargab B. Bhattacharya (ISVLSI, 2014)

A regular network of symmetric functions in quantum-dot cellular automata. - Arighna Deb; Debesh Kumar Das (VDAT, 2014)

A Modular Design to Synthesize Symmetric Functions Using Quantum Quaternary Logic. - Arighna Deb; Debesh Kumar Das; Susmita Sur-Kolay (J. Low Power Electron., 2014)

Boolean Difference Technique for Detecting All Missing Gate Faults in Reversible Circuits. - Joyati Mondal; Bappaditya Mondal; Dipak Kumar Kole; Hafizur Rahaman 001; Debesh K. Das (DDECS, 2015)

Testing of 3D IC with minimum power using genetic algorithm. - Tanusree Kaibartta; Debesh K. Das (IDT, 2015)

An Efficient Reduction of Common Control Lines for Reversible Circuit Optimization. - Arighna Deb; Robert Wille; Rolf Drechsler; Debesh K. Das (ISMVL, 2015)

Squarer design with reduced area and delay. - Arindam Banerjee 003; Debesh Kumar Das (VDAT, 2015)

Partitioning-based test time reduction for core-based 3DICs. - Sabyasachee Banerjee; Subhashis Majumder; Debesh K. Das (VDAT, 2015)

One More Class of Sequential Circuits having Combinational Test Generation Complexity. - Debesh Kumar Das; Hideo Fujiwara (J. Electron. Test., 2015)

The Design of Reversible Signed Multiplier Using Ancient Indian Mathematics. - Arindam Banerjee 003; Debesh Kumar Das (J. Low Power Electron., 2015)

A rule-based approach for minimizing power dissipation of digital circuits. - Subrata Das; Parthasarathi Dasgupta; Petr Fiser; Sudip Ghosh 001; Debesh Kumar Das (DDECS, 2016)

Delay Estimates for Graphene Nanoribbons: A Novel Measure of Fidelity and Experiments with Global Routing Trees. - Subrata Das; Soma Das; Adrija Majumder; Parthasarathi Dasgupta; Debesh Kumar Das (ACM Great Lakes Symposium on VLSI, 2016)

A new ALU architecture design using reversible logic. - Arindam Banerjee 003; Debesh Kumar Das (ISED, 2016)

On the Inadmissible Class of Multiple-Valued Faulty-Functions under Stuck-at Faults. - Debabani Chowdhury; Debesh K. Das; Bhargab B. Bhattacharya; Tsutomu Sasao (ISMVL, 2016)

Double Patterning Lithography (DPL)-compliant layout construction (DCLC) with area-stitch usage tradeoff. - Debasis Pal; Abir Pramanik; Parthasarathi Dasgupta; Debesh Kumar Das (VDAT, 2016)

Squaring in Reversible Logic Using Zero Garbage and Reduced Ancillary Inputs. - Arindam Banerjee 003; Debesh Kumar Das (VLSID, 2016)

A New Squarer design with reduced area and delay. - Arindam Banerjee 003; Debesh Kumar Das (IET Comput. Digit. Tech., 2016)

Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability. - Arighna Deb; Debesh K. Das; Hafizur Rahaman 001; Robert Wille; Rolf Drechsler; Bhargab B. Bhattacharya (ACM J. Emerg. Technol. Comput. Syst., 2016)

Design for Testability Technique of Reversible Logic Circuits Based on Exclusive Testing. - Joyati Mondal; Debesh Kumar Das (ATS, 2017)

A placement optimization technique for 3D IC. - Sabyasachee Banerjee; Subhashis Majumder; Abhishek Varma; Debesh K. Das (ISED, 2017)

A technique to construct global routing trees for graphene nanoribbon (GNR). - Subrata Das; Debesh Kumar Das (ISQED, 2017)

An iterative structure for synthesizing symmetric functions using quantum-dot cellular automata. - Arighna Deb; Debesh K. Das (Microprocess. Microsystems, 2017)

Floorplanning in Graphene Nanoribbon (GNR) Based Circuits. - Subrata Das; Debesh Kumar Das (ISVLSI, 2018)

Optimization of Test Wrapper Length for TSV Based 3D SOCs Using a Heuristic Approach. - Tanusree Kaibartta; Debesh Kumar Das (VDAT, 2018)

Arithmetic Circuits Using Reversible Logic: A Survey Report. - Arindam Banerjee 003; Debesh Kumar Das (ACSS (1), 2019)

Detailed Fault Model for Physical Quantum Circuits. - Arighna Deb; Debesh K. Das (ATS, 2019)

Delay Efficient All Optical Carry Lookahead Adder. - Sayantani Roy; Arighna Deb; Debesh K. Das (VDAT, 2019)

Approach of genetic algorithm for power-aware testing of 3D IC. - Tanusree Kaibartta; Chandan Giri; Hafizur Rahaman 001; Debesh Kumar Das (IET Comput. Digit. Tech., 2019)

Boolean Difference Technique for Detecting All Missing Gate and Stuck-at Faults in Reversible Circuits. - Joyati Mondal; Bappaditya Mondal; Dipak Kumar Kole; Hafizur Rahaman 001; Debesh Kumar Das (J. Circuits Syst. Comput., 2019)

Heuristic Approach for Identification of Random TSV Defects in 3D IC During Pre-bond Testing. - Tanusree Kaibartta; G. P. Biswas; Debesh K. Das (ATS, 2020)

An Improved Online Testing Technique For Reversible Circuits. - Joyati Mondal; Debesh Kumar Das (ISDCS, 2020)

Co-Optimization of Test Wrapper Length and TSV for TSV Based 3D SOCs. - Tanusree Kaibartta; G. P. Biswas; Debesh Kumar Das (J. Electron. Test., 2020)

A Novel ALU Circuit based on Reversible Logic. - Arindam Banerjee 003; Debesh Kumar Das (J. Circuits Syst. Comput., 2020)

A Global Routing Method for Graphene Nanoribbons Based Circuits and Interconnects. - Subrata Das; Debesh Kumar Das; Soumya Pandit (ACM J. Emerg. Technol. Comput. Syst., 2020)

Minimization of Switching Activity of Graphene Based Circuits. - Subrata Das; Petr Fiser; Soumya Pandit; Debesh Kumar Das (VLSID, 2021)

A Genetic Algorithm-Based Metaheuristic Approach for Test Cost Optimization of 3D SIC. - Tanusree Kaibartta; G. P. Biswas; Arup Kumar Pal; Debesh Kumar Das (IEEE Access, 2021)

Fast algorithms for test optimization of core based 3D SoC. - Sabyasachee Banerjee; Subhashis Majumder; Debesh K. Das; Bhargab B. Bhattacharya (Integr., 2021)

An Efficient Design for Testability Approach of Reversible Logic Circuits. - Joyati Mondal; Arighna Deb; Debesh K. Das (J. Circuits Syst. Comput., 2021)

Reliability Aware Global Routing of Graphene Nanoribbon Based Interconnect. - Subrata Das; Debesh Kumar Das; Soumya Pandit (VDAT, 2022)

Easily-Verifiable Design of Non-Scan Sequential Machines for Conformance Checking. - Habibur Rahaman; Santanu Chattopadhyay; Indranil Sengupta 001; Debesh K. Das; Bhargab B. Bhattacharya (VLSID, 2022)

Improved Upper Bound on Independent Domination Number for Hypercubes. - Debabani Chowdhury; Debesh K. Das; Bhargab B. Bhattacharya (CoRR, 2022)

DFT with Universal Test Set for All Missing Gate Faults in Reversible Circuits. - Joyati Mondal; Dipak Kumar Kole; Hafizur Rahaman 001; Debesh Kumar Das; Bhargab B. Bhattacharya (J. Circuits Syst. Comput., 2022)

A new online testing technique for reversible circuits. - Joyati Mondal; Debesh Kumar Das (IET Quantum Commun., 2022)

Fault Testing in AI-Accelerators: A Review. - Bhargab B. Bhattacharya; Debesh K. Das; Subhajit Chatterjee; Hafizur Rahaman 001 (ATS, 2024)

A Novel TSV Repair Framework for 3-D Stacked ICs. - Tanusree Kaibartta; Rajiv Murmu; Debesh Kumar Das (ATS, 2024)

Design Objectives for Synthesis of Graphene PN Junction Circuits Based on Two-Level Representation. - Subrata Das; Arighna Deb; Petr Fiser; Debesh Kumar Das (DSD, 2024)

Leveraging ReRAM Sequence Graphs for Efficient Mapping of Binary Adders in ReRAM Crossbars. - Pragnya Dhal; Arighna Deb; Subrata Das; Debesh Kumar Das (VDAT, 2024)

Genetic Algorithm Based Efficient Grouping Technique for Post Bond Test and Crosstalk Faults Among TSVs. - Tanusree Kaibartta; Hitarth Arora; Debesh Kumar Das (VLSID, 2024)

IRUVD: a new still-image based dataset for automatic vehicle detection. - Asfak Ali; Ram Sarkar; Debesh Kumar Das (Multim. Tools Appl., 2024)

Design-for-testability for reversible logic circuits based on bit-swapping. - Joyati Mondal; Debesh Kumar Das; Bhargab B. Bhattacharya (IET Quantum Commun., 2024)

Power-aware partitioning and test time reduction for 3D-SoC. - Sabyasachee Banerjee; Subhashis Majumder; Bhargab B. Bhattacharya; Debesh K. Das (Innov. Syst. Softw. Eng., 2024)