Chassis: A Platform for Verifying PMU Integration Using Autogenerated Behavioral Models. - Antara Ain; Debjit Pal; Pallab Dasgupta; Siddhartha Mukhopadhyay; Rajdeep Mukhopadhyay; John Gough (ACM Trans. Design Autom. Electr. Syst., 2011)

A Library for Passive Online Verification of Analog and Mixed-Signal Circuits. - Debjit Pal; Pallab Dasgupta; Siddhartha Mukhopadhyay (VLSI Design, 2012)

Using automatically generated invariants for regression testing and bug localization. - Parth Sagdeo; Nicholas Ewalt; Debjit Pal; Shobha Vasudevan (ASE, 2013)

Can't See the Forest for the Trees: State Restoration's Limitations in Post-silicon Trace Signal Selection. - Sai Ma; Debjit Pal; Rui Jiang; Sandip Ray; Shobha Vasudevan (ICCAD, 2015)

Symptomatic Bug Localization for Functional Debug of Hardware Designs. - Debjit Pal; Shobha Vasudevan (VLSID, 2016)

A low cost fully autonomous GPS (Global Positioning System) based quad copter for disaster management. - Himadri Nath Saha; Srijita Basu; Supratim Auddy; Ratul Dey; Arnab Nandy; Debjit Pal; Nirjhar Roy; Subhadeep Jasu; Ankita Saha; Soummyo Priyo Chattopadhyay; Tamanna Maity (CCWC, 2018)

A cloud based autonomous multipurpose system with self-communicating bots and swarm of drones. - Himadri Nath Saha; Nisith K. Das; Susanta K. Pal; Srijita Basu; Supratim Auddy; Ratul Dey; Arnab Nandy; Debjit Pal; Nirjhar Roy; Dipanjan Mitra; Saunak Biswas; Tamanna Maity (CCWC, 2018)

Application level hardware tracing for scaling post-silicon debug. - Debjit Pal; Abhishek Sharma; Sandip Ray; Flavio M. de Paula; Shobha Vasudevan (DAC, 2018)

A figure of merit for assertions in verification. - Samuel Hertz; Debjit Pal; Spencer Offenberger; Shobha Vasudevan (ASP-DAC, 2019)

Scalable functional validation of next generation SoCs - Debjit Pal (2019)

Accurate Operation Delay Prediction for FPGA HLS Using Graph Neural Networks. - Ecenur Ustun; Chenhui Deng; Debjit Pal; Zhijing Li 002; Zhiru Zhang (ICCAD, 2020)

Emphasizing Functional Relevance Over State Restoration in Post-Silicon Signal Tracing. - Debjit Pal; Sai Ma; Shobha Vasudevan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Assertion Ranking Using RTL Source Code Analysis. - Debjit Pal; Spencer Offenberger; Shobha Vasudevan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

GLAIVE: Graph Learning Assisted Instruction Vulnerability Estimation. - Jiajia Jiao; Debjit Pal; Chenhui Deng; Zhiru Zhang (DATE, 2021)

Feature Engineering for Scalable Application-Level Post-Silicon Debugging. - Debjit Pal; Shobha Vasudevan (CoRR, 2021)

Accelerator design with decoupled hardware customizations: benefits and challenges: invited. - Debjit Pal; Yi-Hsiang Lai; Shaojie Xiang; Niansong Zhang; Hongzheng Chen; Jeremy Casas; Pasquale Cocchini; Zhenkun Yang; Jin Yang 006; Louis-Noël Pouchet; Zhiru Zhang (DAC, 2022)

HeteroFlow: An Accelerator Programming Model with Decoupled Data Placement for Software-Defined FPGAs. - Shaojie Xiang; Yi-Hsiang Lai; Yuan Zhou; Hongzheng Chen; Niansong Zhang; Debjit Pal; Zhiru Zhang (FPGA, 2022)

FCCM 2023 PhD Student Forum Compendium of Abstracts: Held on 9th May, 2023, at Los Angeles, USA. - Debjit Pal (FCCM, 2023)

VeriBug: An Attention-Based Framework for Bug Localization in Hardware Designs. - Giuseppe Stracquadanio; Sourav Medya; Stefano Quer; Debjit Pal (DATE, 2024)

Formal Verification of Source-to-Source Transformations for HLS. - Louis-Noël Pouchet; Emily Tucker; Niansong Zhang; Hongzheng Chen; Debjit Pal; Gabriel Rodríguez 001; Zhiru Zhang (FPGA, 2024)

DETECTive: Machine Learning-driven Automatic Test Pattern Prediction for Faults in Digital Circuits. - Vincenzo Petrolo; Sourav Medya; Mariagrazia Graziano; Debjit Pal (ACM Great Lakes Symposium on VLSI, 2024)

Prioritizing Information Flow Violations: Generation of Ranked Security Assertions for Hardware Designs. - Avinash Ayalasomayajula; Nusrat Farzana; Debjit Pal; Farimah Farahmandi (HOST, 2024)

Hopf bifurcation and patterns formation in a diffusive two prey-one predator system with fear in preys and help. - Debjit Pal; Santu Ghorai; Dipak Kesh; Debasis Mukherjee (Appl. Math. Comput., 2024)

Cross-diffusion mediated Spatiotemporal patterns in a predator-prey system with hunting cooperation and fear effect. - Debjit Pal; Dipak Kesh; Debasis Mukherjee (Math. Comput. Simul., 2024)

SCAR: Power Side-Channel Analysis at RTL Level. - Amisha Srivastava; Sanjay Das; Navnil Choudhury; Rafail Psiakis; Pedro Henrique Silva; Debjit Pal; Kanad Basu (IEEE Trans. Very Large Scale Integr. Syst., 2024)

ARISTOTLE: Feature Engineering for Scalable Application-Level Post-Silicon Debugging. - Debjit Pal; Shobha Vasudevan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Energy Efficient Compact Approximate Multiplier for Error-Resilient Applications. - Ayoub Sadeghi; Rami Rasheedi; Inna Partin-Vaisband; Debjit Pal (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Are LLMs Ready for Practical Adoption for Assertion Generation? - Vaishnavi Pulavarthi; Deeksha Nandal; Soham Dan; Debjit Pal (DATE, 2025)

AssertionBench: A Benchmark to Evaluate Large-Language Models for Assertion Generation. - Vaishnavi Pulavarthi; Deeksha Nandal; Soham Dan; Debjit Pal (NAACL (Findings), 2025)

Dynamics of a Predator-Prey Model with Fear and Its Carryover Effects, Allee in Predator and Diffusion-Driven Patterns. - Debjit Pal; Dipak Kesh; Debasis Mukherjee (Int. J. Bifurc. Chaos, 2025)

PoSyn: Secure Power Side-Channel Aware Synthesis. - Amisha Srivastava; Samit Shahnawaz Miftah; Hyunmin Kim; Debjit Pal; Kanad Basu (CoRR, 2025)

HERCULES: Hardware accElerator foR stoChastic schedULing in hEterogeneous Systems. - Vairavan Palaniappan; Adam H. Ross; Amit Ranjan Trivedi; Debjit Pal (CoRR, 2025)