An algorithm for trading off quantization error with hardware resources for MATLAB based FPGA design. - Sanghamitra Roy; Debjit Sinha; Prithviraj Banerjee (FPGA, 2004)

Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation. - Debjit Sinha; Hai Zhou 001 (ICCAD, 2004)

Optimal gate sizing for coupling-noise reduction. - Debjit Sinha; Hai Zhou 001; Chris C. N. Chu (ISPD, 2004)

Yield driven gate sizing for coupling-noise reduction under uncertainty. - Debjit Sinha; Hai Zhou 001 (ASP-DAC, 2005)

Statistical gate sizing for timing yield optimization. - Debjit Sinha; Narendra V. Shenoy; Hai Zhou 001 (ICCAD, 2005)

A unified framework for statistical timing analysis with coupling and multiple input switching. - Debjit Sinha; Hai Zhou 001 (ICCAD, 2005)

Smart bit-width allocation for low power optimization in a systemc based ASIC design environment. - Arindam Mallik; Debjit Sinha; Prithviraj Banerjee; Hai Zhou 001 (DATE, 2006)

Advances in Computation of the Maximum of a Set of Random Variables. - Debjit Sinha; Hai Zhou 001; Narendra V. Shenoy (ISQED, 2006)

Yield-Aware Cache Architectures. - Serkan Ozdemir; Debjit Sinha; Gokhan Memik; Jonathan Adams; Hai Zhou 001 (MICRO, 2006)

Gate-size optimization under timing constraints for coupling-noise reduction. - Debjit Sinha; Hai Zhou 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Statistical Timing Analysis With Coupling. - Debjit Sinha; Hai Zhou 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Statistical Timing Yield Optimization by Gate Sizing. - Debjit Sinha; Narendra V. Shenoy; Hai Zhou 001 (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. - Debjit Sinha; Jianfeng Luo 001; Subramanian Rajagopalan; Shabbir H. Batterywala; Narendra V. Shenoy; Hai Zhou 001 (VLSI Design, 2007)

Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment. - Arindam Mallik; Debjit Sinha; Prithviraj Banerjee; Hai Zhou 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Advances in Computation of the Maximum of a Set of Gaussian Random Variables. - Debjit Sinha; Hai Zhou 001; Narendra V. Shenoy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Driver waveform computation for timing analysis with multiple voltage threshold driver models. - Peter Feldmann; Soroush Abbaspour; Debjit Sinha; Gregory Schaeffer; Revanta Banerji; Hemlata Gupta (DAC, 2008)

Constrained aggressor set selection for maximum coupling noise. - Debjit Sinha; Gregory Schaeffer; Soroush Abbaspour; Alex Rubin; Frank Borkam (ICCAD, 2008)

Feasible Aggressor-Set Identification Under Constraints for Maximum Coupling Noise. - Debjit Sinha; Alex Rubin; Chandu Visweswariah; Frank Borkam; Gregory Schaeffer; Soroush Abbaspour (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

A Timing-Dependent Power Estimation Framework Considering Coupling. - DiaaEldin Khalil; Debjit Sinha; Hai Zhou 001; Yehea I. Ismail (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Reversible statistical max/min operation: concept and applications to timing. - Debjit Sinha; Chandu Visweswariah; Natesan Venkateswaran; Jinjun Xiong; Vladimir Zolotov (DAC, 2012)

Timing analysis with nonseparable statistical and deterministic variations. - Vladimir Zolotov; Debjit Sinha; Jeffrey G. Hemmett; Eric A. Foreman; Chandu Visweswariah; Jinjun Xiong; Jeremy Leitzen; Natesan Venkateswaran (DAC, 2012)

Speeding up computation of the max/min of a set of gaussians for statistical timing analysis and optimization. - Vimitha A. Kuruvilla; Debjit Sinha; Jeff Piaget; Chandu Visweswariah; Nitin Chandrachoodan (DAC, 2013)

TAU 2013 variation aware timing analysis contest. - Debjit Sinha; Luís Guerra e Silva; Jia Wang; Shesha Raghunathan; Dileep Netrabile; Ahmed Shebaita (ISPD, 2013)

TAU 2014 contest on removing common path pessimism during timing analysis. - Jin Hu; Debjit Sinha; Igor Keller (ICCAD, 2014)

A distributed timing analysis framework for large designs. - Tsung-Wei Huang; Martin D. F. Wong; Debjit Sinha; Kerim Kalafala; Natesan Venkateswaran (DAC, 2016)

Statistical path tracing in timing graphs. - Vasant Rao; Debjit Sinha; Nitin Srimal; Prabhat K. Maurya (DAC, 2016)

Practical statistical static timing analysis with current source models. - Debjit Sinha; Vladimir Zolotov; Sheshashayee K. Raghunathan; Michael H. Wood; Kerim Kalafala (DAC, 2016)

Generation and use of statistical timing macro-models considering slew and load variability. - Debjit Sinha; Vladimir Zolotov; Jin Hu; Sheshashayee K. Raghunathan; Adil Bhanji; Christine M. Casey (ICCAD, 2016)

Sharing and Re-use of Statistical Timing Macro-Models across Multiple Voltage Domains. - Debjit Sinha; Vladimir Zolotov; Eric Fluhr; Michael H. Wood; Jeffrey Ritzinger; Natesan Venkateswaran; Stephen Shuma (VLSID, 2016)

Statistical Timing Analysis considering Multiple-Input Switching. - Debjit Sinha; Vasant Rao; Chaitanya Peddawad; Michael H. Wood; Jeffrey G. Hemmett; Suriya Skariah; Patrick Williams (DAC, 2020)

Technology Lookup Table based Default Timing Assertions for Hierarchical Timing Closure. - Ravi Ledalla; Debjit Sinha; Adil Bhanji; Chaobo Li; Gregory Schaeffer; Hemlata Gupta; Jennifer Basile (DATE, 2021)