The Need for Reconfigurable Routers in Networks-on-Chip. - Debora Matos; Caroline Concatto; Luigi Carro; Fernanda Lima Kastensmidt; Altamiro Amadeu Susin (ARC, 2009)

NoC Power Optimization Using a Reconfigurable Router. - Caroline Concatto; Debora Matos; Luigi Carro; Fernanda Lima Kastensmidt; Altamiro Amadeu Susin; Márcio Eduardo Kreutz (ISVLSI, 2009)

Adaptive router architecture based on traffic behavior observability. - Debora Matos; Caroline Concatto; Anelise Kologeski; Luigi Carro; Fernanda Lima Kastensmidt; Altamiro Amadeu Susin; Márcio Eduardo Kreutz (NoCArc@MICRO, 2009)

Fault tolerant mechanism to improve yield in NoCs using a reconfigurable router. - Caroline Concatto; Debora Matos; Luigi Carro; Fernanda Lima Kastensmidt; Altamiro Amadeu Susin; Érika F. Cota; Márcio Eduardo Kreutz (SBCCI, 2009)

Associating packets of heterogeneous cores using a synchronizer wrapper for NoCs. - Debora Matos; Luigi Carro; Altamiro Amadeu Susin (ISCAS, 2010)

Monitor-adapter coupling for NOC performance tuning. - Debora Matos; Caroline Concatto; Anelise Kologeski; Luigi Carro; Fernanda Lima Kastensmidt; Altamiro Amadeu Susin; Márcio Eduardo Kreutz (ICSAMOS, 2010)

Network interface to synchronize multiple packets on NoC-based Systems-on-Chip. - Debora Matos; Miklecio Costa; Luigi Carro; Altamiro Amadeu Susin (VLSI-SoC, 2010)

A new reconfigurable clock-gating technique for low power SRAM-based FPGAs. - Luca Sterpone; Luigi Carro; Debora Matos; Stephan Wong; F. Fakhar (DATE, 2011)

Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip. - Debora Matos; Gianluca Palermo; Vittorio Zaccaria; Cezar Reinbrecht; Altamiro Amadeu Susin; Cristina Silvano; Luigi Carro (NoCArc@MICRO, 2011)

Reconfigurable Routers for Low Power and High Performance. - Debora Matos; Caroline Concatto; Márcio Eduardo Kreutz; Fernanda Lima Kastensmidt; Luigi Carro; Altamiro Amadeu Susin (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Floorplan-aware hierarchical NoC topology with GALS interfaces. - Debora Matos; Cezar Reinbrecht; Gianluca Palermo; Jonathan Martinelli; Altamiro Amadeu Susin; Cristina Silvano; Luigi Carro (ISCAS, 2012)

Hierarchical and Multiple Switching NoC with Floorplan Based Adaptability. - Debora Matos; Cezar Reinbrecht; Márcio Eduardo Kreutz; Gianluca Palermo; Luigi Carro; Altamiro Amadeu Susin (ARC, 2013)

Combining fault tolerance and serialization effort to improve yield in 3D Networks-on-Chip. - Anelise Kologeski; Caroline Concatto; Debora Matos; Daniel Grehs; Tiago Motta; Felipe Almeida; Fernanda Lima Kastensmidt; Altamiro Amadeu Susin; Ricardo Reis 001 (ICECS, 2013)

A power-efficient hierarchical network-on-chip topology for stacked 3D ICs. - Debora Matos; Cezar Reinbrecht; Tiago Motta; Altamiro Amadeu Susin (VLSI-SoC, 2013)

A NOC closed-loop performance monitor and adapter. - Debora Matos; Caroline Concatto; Anelise Kologeski; Luigi Carro; Márcio Eduardo Kreutz; Fernanda Gusmão de Lima Kastensmidt; Altamiro Amadeu Susin (Microprocess. Microsystems, 2013)

Adaptive multiple switching strategy toward an ideal NoC. - Debora Matos; Márcio Eduardo Kreutz; Cezar Reinbrecht; Luigi Carro; Altamiro Amadeu Susin (ISCAS, 2014)

Performance evaluation of hierarchical NoC topologies for stacked 3D ICs. - Debora Matos; Max Prass; Márcio Eduardo Kreutz; Luigi Carro; Altamiro Amadeu Susin (ISCAS, 2015)

Evaluation of emerging TSV-enabled main memories on the PARSEC benchmark. - Rodrigo Cataldo; Guilherme Korol; Ramon Fernandes; Gustavo Sanchez; Debora Matos; César A. M. Marcon (ICECS, 2016)

Architectural exploration of Last-Level Caches targeting homogeneous multicore systems. - Rodrigo Cataldo; Guilherme Korol; Ramon Fernandes; Debora Matos; César A. M. Marcon (SBCCI, 2016)

3D MPSoC with On-Chip Cache Support - Design and Exploitation. - Rodrigo Cataldo; César A. M. Marcon; Debora Matos (CoRR, 2025)