Challenges in designing high speed memory subsystem for mobile applications. - Tsunwai Gary Yip; Philip Yeung; Ming Li; Deborah Dressler (DATE, 2011)

A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface. - Amir Amirkhany; Jason Wei; Navin K. Mishra; Jie Shen 010; Wendemagegnehu T. Beyene; Catherine Chen 005; T. J. Chin; Deborah Dressler; Charlie Huang; Vijay P. Gadde; Mohammad Hekmat; Kambiz Kaviani; et al. (IEEE J. Solid State Circuits, 2012)

A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface. - Kambiz Kaviani; Ting Wu 003; Jason Wei; Amir Amirkhany; Jie Shen 010; T. J. Chin; Chintan Thakkar; Wendemagegnehu T. Beyene; Norman Chan; Catherine Chen 005; Bing Ren Chuang; Deborah Dressler; et al. (IEEE J. Solid State Circuits, 2012)

An Adaptive Body-Biased Clock Generation System in 28nm CMOS. - Makarand Shirasgaonkar; Roxanne Vu; Deborah Dressler; Nhat Nguyen; Kambiz Kaviani; Yueyong Wang (VLSID, 2014)