Increasing the Instruction Fetch Rate via Multiple Branch Prediction and a Branch Address Cache. - Tse-Yu Yeh; Deborah T. Marr; Yale N. Patt (International Conference on Supercomputing, 1993)

Multiprocessor Validation of the Pentium® Pro Microprocessor. - Deborah T. Marr; Shreekant S. Thakkar; Richard Zucker (COMPCON, 1996)

Multiprocessor Validation of the Pentium Pro. - Deborah T. Marr; Subramanian Natarajan; Shreekant S. Thakkar; Richard Zucker (Computer, 1996)

Hyperthreading Technology in the Netburst Microarchitecture. - David A. Koufaty; Deborah T. Marr (IEEE Micro, 2003)

Microarchitecture Choices and Tradeoffs for Maximizing Processing Efficiency. - Deborah T. Marr (2008)

Author retrospective for increasing the instruction fetch rate via multiple branch prediction and a branch address cache. - Tse-Yu Yeh; Deborah T. Marr; Yale N. Patt (ICS 25th Anniversary, 2014)