A direct-conversion receiver for DVB-H. - Patrick Antoine; Philippe Bauser; Hugues Beaulaton; Martin Buchholz; Declan Carey; Thierry Cassagnes; T. K. Chan; Stephane Colomines; Fionn Hurley; David T. Jobling; Niall Kearney; Aidan C. Murphy; et al. (IEEE J. Solid State Circuits, 2005)

Wideband flexible-reach techniques for a 0.5-16.3Gb/s fully-adaptive transceiver in 20nm CMOS. - Jafar Savoj; Hesam Amir Aslanzadeh; Declan Carey; Marc Erett; Wayne Fang; Yohan Frans; Kenny C.-H. Hsieh; Jay Im; Anup P. Jose; Didem Turker; Parag Upadhyaya; Zhaoyin Daniel Wu; et al. (CICC, 2014)

A 0.5-16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS. - Yohan Frans; Declan Carey; Marc Erett; Hesam Amir Aslanzadeh; Wayne Y. Fang; Didem Turker; Anup P. Jose; Adebabay Bekele; Jay Im; Parag Upadhyaya; Zhaoyin Daniel Wu; Kenny C.-H. Hsieh; et al. (IEEE J. Solid State Circuits, 2015)

A 0.5-16.3Gbps multi-standard serial transceiver with 219mW/channel in 16nm FinFET. - Marc Erett; James Hudner; Declan Carey; Ronan Casey; Kevin Geary; Kay Hearne; Pedro Neto 001; Thomas Mallard; Vikas Sooden; Mark Smyth; Yohan Frans; Jay Im; et al. (ESSCIRC, 2016)

A 0.5-16.3 Gbps Multi-Standard Serial Transceiver With 219 mW/Channel in 16-nm FinFET. - Marc Erett; James Hudner; Declan Carey; Ronan Casey; Kevin Geary; Kay Hearne; Pedro Neto 001; Thomas Mallard; Vikas Sooden; Mark Smyth; Yohan Frans; Jay Im; et al. (IEEE J. Solid State Circuits, 2017)

A 126mW 56Gb/s NRZ wireline transceiver for synchronous short-reach applications in 16nm FinFET. - Marc Erett; Declan Carey; James Hudner; Ronan Casey; Kevin Geary; Pedro Neto 001; Mayank Raj; Scott McLeod; Hongtao Zhang 002; Arianne Roldan; Hongyuan Zhao; Ping-Chuan Chiang; et al. (ISSCC, 2018)

A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET. - James Hudner; Declan Carey; Ronan Casey; Kay Hearne; Pedro Wilson de Abreu Farias Neto; Ilias Chlis; Marc Erett; Chi Fung Poon; Asma Laraba; Hongtao Zhang 002; Sai Lalith Chaitanya Ambatipudi; David Mahashin; et al. (VLSI Circuits, 2018)

A 112-GB/S PAM4 Transmitter in 16NM FinFET. - Kee Hian Tan; Ping-Chuan Chiang; Yipeng Wang 003; Haibing Zhao; Arianne Roldan; Hongyuan Zhao; Nakul Narang; Siok-Wei Lim; Declan Carey; Sai Lalith Chaitanya Ambatipudi; Parag Upadhyaya; Yohan Frans; et al. (VLSI Circuits, 2018)

A 2.25pJ/bit Multi-lane Transceiver for Short Reach Intra-package and Inter-package Communication in 16nm FinFET. - Marc Erett; Declan Carey; Ronan Casey; James Hudner; Kevin Geary; Ted Lee; Mayank Raj; Hongtao Zhang 002; Arianne Roldan; Hongyuan Zhao; Ping-Chuan Chiang; Haibing Zhao; et al. (CICC, 2019)

6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET. - Jay Im; Kevin Zheng; Adam Chou; Lei Zhou; Jae Wook Kim; Stanley Chen; Yipeng Wang 003; Hao-Wei Hung; Kee Hian Tan; Winson Lin; Arianne Roldan; Declan Carey; et al. (ISSCC, 2020)

A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET. - Jay Im; Kevin Zheng; Chuen-Huei Adam Chou; Lei Zhou; Jae Wook Kim; Stanley Chen; Yipeng Wang 003; Hao-Wei Hung; Kee Hian Tan; Winson Lin; Arianne Roldan; Declan Carey; et al. (IEEE J. Solid State Circuits, 2021)