AES crypto chip utilizing high-speed parallel pipelined architecture. - Deen Kotturi; Seong-Moo Yoo; John Blizzard (ISCAS (5), 2005)

An AES crypto chip using a high-speed parallel pipelined architecture. - Seong-Moo Yoo; Deen Kotturi; W. David Pan; John Blizzard (Microprocess. Microsystems, 2005)