O(1) Parallel Time Incremental Graph Algorithms. - Deepak D. Sherlekar; Shaunak Pawagi; I. V. Ramakrishnan (FSTTCS, 1985)

Input Sensitive VLSI Layouts for Graphs of Arbitrary Degree. - Deepak D. Sherlekar; Joseph F. JáJá (AWOC, 1988)

Optimality of Gauge and Degree-Sensitive VLSI Layouts of Planar Graphs. - Deepak D. Sherlekar (ICCI, 1990)

Design planning for high-performance ASICs. - John Y. Sayah; Rajesh Gupta; Deepak D. Sherlekar; Philip S. Honsinger; Jitendra M. Apte; S. Wayne Bollinger; Hai Hsia Chen; Sumit DasGupta; Edward P. Hsieh; Andrew D. Huber; Edward J. Hughes; Zahi M. Kurzum; et al. (IBM J. Res. Dev., 1996)

Design considerations for regular fabrics. - Deepak D. Sherlekar (ISPD, 2004)

Late Breaking Results: On the One-Key Premise of Logic Locking. - Yinghua Hu; Hari Cherupalli; Mike Borza; Deepak D. Sherlekar (DAC, 2024)