An MC-SS Platform for Short-Range Communications in the Personal Network Context. - Dominique Noguet; Marc Laugeois; Xavier Popon; B. Balamuralidhar; Manuel Lobeira; Narasimha Sortur; Deepak Dasalukunte; Cedric Dehos; Zeta Bakirtzoglou (EURASIP J. Wirel. Commun. Netw., 2008)

Transmitter Architecture for Faster-than-Nyquist Signaling Systems. - Deepak Dasalukunte; Fredrik Rusek; John B. Anderson; Viktor Öwall (ISCAS, 2009)

An Iterative Decoder for Multicarrier Faster-Than-Nyquist Signaling Systems. - Deepak Dasalukunte; Fredrik Rusek; Viktor Öwall (ICC, 2010)

Design and Implementation of Iterative Decoder for Faster-than-Nyquist Signaling Multicarrier Systems. - Deepak Dasalukunte; Fredrik Rusek; John B. Anderson; Viktor Öwall (ISVLSI, 2011)

Improved Memory Architecture for Multicarrier Faster-than-Nyquist Iterative Decoder. - Deepak Dasalukunte; Fredrik Rusek; Viktor Öwall (ISVLSI, 2011)

Complexity analysis of IOTA filter architectures in faster-than-Nyquist multicarrier systems. - Deepak Dasalukunte; Shahid Mehmood; Viktor Öwall (NORCHIP, 2011)

Multicarrier Faster-Than-Nyquist Transceivers: Hardware Architecture and Performance Analysis. - Deepak Dasalukunte; Fredrik Rusek; Viktor Öwall (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

A 0.8 mm2 9.6 mW implementation of a multicarrier Faster-than-Nyquist signaling iterative decoder in 65nm CMOS. - Deepak Dasalukunte; Fredrik Rusek; Viktor Öwall (ESSCIRC, 2012)

An 0.8-mm2 9.6-mW Iterative Decoder for Faster-Than-Nyquist and Orthogonal Signaling Multicarrier Systems in 65-nm CMOS. - Deepak Dasalukunte; Fredrik Rusek; Viktor Öwall (IEEE J. Solid State Circuits, 2013)

Hardware Architecture of IOTA Pulse Shaping Filters for Multicarrier Systems. - Shahid Mehmood; Deepak Dasalukunte; Viktor Öwall (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Adaptive and multi-mode baseband systems for next generation wireless communication. - Farhana Sheikh; Ankit Sharma; Oskar Andersson; Mehnaz Rahman; Dongmin Yoon; Alexios Balatsoukas-Stimming; Deepak Dasalukunte; Anthony Chun (ACSSC, 2017)

An Ultra-Low Power, Fully Integrated Wake-Up Receiver and Digital Baseband with All-Digital Impairment Correction and -92.4dBm Sensitivity for 802.11ba. - Richard Dorrance; Renzhi Liu; K. T. Asma Beevi; Deepak Dasalukunte; Mario A. Santana Lopez; Vinod Kristem; Shahrnaz Azizi; Brent R. Carlton (VLSI Circuits, 2019)

An 802.11ba-Based Wake-Up Radio Receiver With Wi-Fi Transceiver Integration. - Renzhi Liu; K. T. Asma Beevi; Richard Dorrance; Deepak Dasalukunte; Vinod Kristem; Mario A. Santana Lopez; Alexander W. Min; Shahrnaz Azizi; Minyoung Park; Brent R. Carlton (IEEE J. Solid State Circuits, 2020)

A Vector Processor for Mean Field Bayesian Channel Estimation. - Deepak Dasalukunte; Richard Dorrance; Le Liang; Lu Lu 002 (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference. - Hechen Wang; Renzhi Liu; Richard Dorrance; Deepak Dasalukunte; Xiaosen Liu; Dan Lake; Brent R. Carlton; May Wu (VLSI Technology and Circuits, 2022)

Low latency communication over commercially available LTE and remote driving. - Andrey Belogolovy; Deepak Dasalukunte; Richard Dorrance; Evgeny Stupachenko; Xue Zhang (CoRR, 2022)

A Charge Domain SRAM Compute-in-Memory Macro With C-2C Ladder-Based 8-Bit MAC Unit in 22-nm FinFET Process for Edge Inference. - Hechen Wang; Renzhi Liu; Richard Dorrance; Deepak Dasalukunte; Dan Lake; Brent R. Carlton (IEEE J. Solid State Circuits, 2023)

An Energy-Efficient Bayesian Neural Network Accelerator With CiM and a Time-Interleaved Hadamard Digital GRNG Using 22-nm FinFET. - Richard Dorrance; Deepak Dasalukunte; Hechen Wang; Renzhi Liu; Brent R. Carlton (IEEE J. Solid State Circuits, 2023)

A PVT Robust 8-Bit Signed Analog Compute-In-Memory Accelerator with Integrated Activation Functions for AI Applications. - Hechen Wang; Renzhi Liu; Richard Dorrance; Deepak Dasalukunte; Niranjan Gowda; Brent R. Carlton (VLSI Technology and Circuits, 2024)