Protecting Ownership of Reusable IP Core Generated during High Level Synthesis. - Deepak Kachave; Anirban Sengupta (iNIS, 2016)

Generating Multi-cycle and Multiple Transient Fault Resilient Design During Physically Aware High Level Synthesis. - Anirban Sengupta; Deepak Kachave (ISVLSI, 2016)

Integrating physical level design and high level synthesis for simultaneous multi-cycle transient and multiple transient fault resiliency of application specific datapath processors. - Deepak Kachave; Anirban Sengupta (Microelectron. Reliab., 2016)

Reliability and Threat Analysis of NBTI Stress on DSP Cores. - Anirban Sengupta; Deepak Kachave; Shubha Neema; Panugothu Sri Harsha (iNIS, 2017)

Low cost fault tolerance against kc-cycle and km-unit transient for loop based control data flow graphs during physically aware high level synthesis. - Anirban Sengupta; Deepak Kachave (Microelectron. Reliab., 2017)

Integrating Compiler Driven Transformation and Simulated Annealing Based Floorplan for Optimized Transient Fault Tolerant DSP Cores. - Anirban Sengupta; Deepak Kachave (iSES, 2018)

Shielding CE Hardware Against Reverse-Engineering Attacks Through Functional Locking [Hardware Matters]. - Deepak Kachave; Anirban Sengupta (IEEE Consumer Electron. Mag., 2018)

Forensic engineering for resolving ownership problem of reusable IP core generated during high level synthesis. - Anirban Sengupta; Deepak Kachave (Future Gener. Comput. Syst., 2018)

Effect of NBTI stress on DSP cores used in CE devices: threat model and performance estimation. - Deepak Kachave; Anirban Sengupta; Shubha Neema; Panugothu Sri Harsha (IET Comput. Digit. Tech., 2018)

Spatial and Temporal Redundancy for Transient Fault-Tolerant Datapath. - Anirban Sengupta; Deepak Kachave (IEEE Trans. Aerosp. Electron. Syst., 2018)

Low Cost Functional Obfuscation of Reusable IP Ores Used in CE Hardware Through Robust Locking. - Anirban Sengupta; Deepak Kachave; Dipanjan Roy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)