Parallel Programming of Resistive Cross-point Array for Synaptic Plasticity. - Zihan Xu; Abinash Mohanty; Pai-Yu Chen; Deepak Kadetotad; Binbin Lin; Jieping Ye; Sarma B. K. Vrudhula; Shimeng Yu; Jae-sun Seo; Yu Cao 001 (BICA, 2014)

Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning. - Deepak Kadetotad; Zihan Xu; Abinash Mohanty; Pai-Yu Chen; Binbin Lin; Jieping Ye; Sarma B. K. Vrudhula; Shimeng Yu; Yu Cao 001; Jae-sun Seo (BioCAS, 2014)

Face recognition using transform domain feature extraction and PSO-based feature selection. - N. L. Ajit Krisshna; Deepak Vinayak Kadetotad; K. Manikantan; S. Ramachandran (Appl. Soft Comput., 2014)

Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip. - Pai-Yu Chen; Deepak Kadetotad; Zihan Xu; Abinash Mohanty; Binbin Lin; Jieping Ye; Sarma B. K. Vrudhula; Jae-sun Seo; Yu Cao 001; Shimeng Yu (DATE, 2015)

Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration. - Deepak Kadetotad; Zihan Xu; Abinash Mohanty; Pai-Yu Chen; Binbin Lin; Jieping Ye; Sarma B. K. Vrudhula; Shimeng Yu; Yu Cao 001; Jae-sun Seo (IEEE J. Emerg. Sel. Topics Circuits Syst., 2015)

Efficient memory compression in deep neural networks using coarse-grain sparsification for speech applications. - Deepak Kadetotad; Sairam Arunachalam; Chaitali Chakrabarti; Jae-sun Seo (ICCAD, 2016)

Comprehensive Evaluation of OpenCL-based Convolutional Neural Network Accelerators in Xilinx and Altera FPGAs. - Ricardo Tapiador; Antonio Rios-Navarro; Alejandro Linares-Barranco; Minkyu Kim 001; Deepak Kadetotad; Jae-sun Seo (CoRR, 2016)

A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS. - Minkyu Kim 001; Abinash Mohanty; Deepak Kadetotad; Naveen Suda; Luning Wei; Pooja Saseendran; Xiaofei He 001; Yu Cao 001; Jae-sun Seo (ASP-DAC, 2017)

Low-power neuromorphic speech recognition engine with coarse-grain sparsity. - Shunti Yin; Deepak Kadetotad; Bonan Yan; Chang Song 001; Yiran Chen 001; Chaitali Chakrabarti; Jae-sun Seo (ASP-DAC, 2017)

Monolithic 3D IC designs for low-power deep neural networks targeting speech recognition. - Kyungwook Chang; Deepak Kadetotad; Yu Cao 001; Jae-sun Seo; Sung Kyu Lim (ISLPED, 2017)

Comprehensive Evaluation of OpenCL-Based CNN Implementations for FPGAs. - Ricardo Tapiador-Morales; Antonio Rios-Navarro; Alejandro Linares-Barranco; Minkyu Kim 001; Deepak Kadetotad; Jae-sun Seo (IWANN (2), 2017)

Power, Performance, and Area Benefit of Monolithic 3D ICs for On-Chip Deep Neural Networks Targeting Speech Recognition. - Kyungwook Chang; Deepak Kadetotad; Yu Cao 001; Jae-sun Seo; Sung Kyu Lim (ACM J. Emerg. Technol. Comput. Syst., 2018)

A 8.93-TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity With All Parameters Stored On-Chip. - Deepak Kadetotad; Visar Berisha; Chaitali Chakrabarti; Jae-Sun Seo (ESSCIRC, 2019)

Joint Optimization of Quantization and Structured Sparsity for Compressed Deep Neural Networks. - Gaurav Srivastava 001; Deepak Kadetotad; Shihui Yin; Visar Berisha; Chaitali Chakrabarti; Jae-sun Seo (ICASSP, 2019)

Neuromorphic Hardware Accelerator for SNN Inference based on STT-RAM Crossbar Arrays. - Shruti R. Kulkarni; Deepak Vinayak Kadetotad; Shihui Yin; Jae-Sun Seo; Bipin Rajendran (ICECS, 2019)

ECG Authentication Neural Network Hardware Design with Collective Optimization of Low Precision and Structured Compression. - Sai Kiran Cherupally; Gaurav Srivastava 001; Shihui Yin; Deepak Kadetotad; Chisung Bae; Sang Joon Kim; Jae-sun Seo (ISCAS, 2019)

A 1.06- $ mu$ W Smart ECG Processor in 65-nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring. - Shihui Yin; Minkyu Kim 001; Deepak Kadetotad; Yang Liu; Chisung Bae; Sang Joon Kim; Yu Cao 001; Jae-sun Seo (IEEE J. Solid State Circuits, 2019)

A Real-Time 17-Scale Object Detection Accelerator With Adaptive 2000-Stage Classification in 65 nm CMOS. - Minkyu Kim 001; Abinash Mohanty; Deepak Kadetotad; Luning Wei; Xiaofei He 001; Yu Cao 001; Jae-sun Seo (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

On-Chip Learning and Inference Acceleration of Sparse Representations. - Deepak Kadetotad (2019)

Compressing LSTM Networks with Hierarchical Coarse-Grain Sparsity. - Deepak Kadetotad; Jian Meng; Visar Berisha; Chaitali Chakrabarti; Jae-sun Seo (INTERSPEECH, 2020)

A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV, and SRAM PUF for Authentication and Secret Key Generation. - Sai Kiran Cherupally; Shihui Yin; Deepak Kadetotad; Chisung Bae; Sang Joon Kim; Jae-sun Seo (IEEE J. Solid State Circuits, 2020)

An 8.93 TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity for On-Device Speech Recognition. - Deepak Kadetotad; Shihui Yin; Visar Berisha; Chaitali Chakrabarti; Jae-sun Seo (IEEE J. Solid State Circuits, 2020)

ECG Authentication Hardware Design With Low-Power Signal Processing and Neural Network Optimization With Low Precision and Structured Compression. - Sai Kiran Cherupally; Shihui Yin; Deepak Kadetotad; Gaurav Srivastava 001; Chisung Bae; Sang Joon Kim; Jae-sun Seo (IEEE Trans. Biomed. Circuits Syst., 2020)

Quality and Complexity Tradeoffs for DNN-Based Binaural Speech Enhancement in Hearing Aids. - Parth Mishra; Deepak Kadetotad; Eric A. Durant; Terence Betlehem; Martin F. McKinney (ICASSP, 2025)