An 8-bit 20.7 TOPS/W Multi-Level Cell ReRAM-based Compute Engine. - Justin M. Correll; Lu Jie 001; Seungheun Song; Seungjong Lee; Junkang Zhu; Wei Tang 010; Luke Wormald; Jack Erhardt; Nicolas Breil; Roger Quon; Deepak Kamalanathan; Siddarth A. Krishnan; et al. (VLSI Technology and Circuits, 2022)

A Fully Integrated System-on-Chip Design with Scalable Resistive Random-Access Memory Tile Design for Analog in-Memory Computing. - Fuxi Cai; She-Hwa Yen; Apurva Uppala; Luke Thomas; Tianchi Liu 003; Peter Fu; Xiaofeng Zhang; Ambrose Low; Deepak Kamalanathan; Joe Hsu; Buvna Ayyagari-Sangamalli (Adv. Intell. Syst., 2022)

Self-rectifying non-volatile tunneling synapse: multiscale modeling augmented development. - Bastien Beltrando; Marco A. Villena; Mondol Anik Kumar; Shruba Gangopadhyay; Deepak Kamalanathan; E. Smith; Nasrin Kazem; Ghazal Saheli; Stephen Weeks; Michael Haverty; Muthukumar Kaliappan; Andrea Padovani; et al. (IMW, 2024)

An 8-bit 20.7 TOPS/W Multilevel Cell ReRAM Macro With ADC-Assisted Bit-Serial Processing. - Justin M. Correll; Lu Jie 001; Seungheun Song; Seungjong Lee; Junkang Zhu; Wei Tang 010; Luke Wormald; Jack Erhardt; Nicolas Breil; Roger Quon; Deepak Kamalanathan; Siddarth A. Krishnan; et al. (IEEE J. Solid State Circuits, 2025)