A Functional Programming Framework of Heterogeneous Model of Computation for System Design. - Deepak Mathaikutty; Hiren D. Patel; Sandeep K. Shukla (FDL, 2004)

Effects of property ordering in an incremental formal modeling methodology. - Syed Suhaib; Deepak Mathaikutty; Sandeep K. Shukla (HLDVT, 2004)

Extreme Formal Modeling (XFM) for Hardware Models. - Syed Suhaib; Deepak Mathaikutty; Sandeep K. Shukla; David Berner (MTV, 2004)

SystemCXML: An Exstensible SystemC Front end Using XML. - David Berner; Jean-Pierre Talpin; Hiren D. Patel; Deepak Mathaikutty; Sandeep K. Shukla (FDL, 2005)

Modelling Environment for Heterogeneous Systems based on MoCs. - Deepak Mathaikutty; Hiren D. Patel; Sandeep K. Shukla; Axel Jantsch (FDL, 2005)

Automated Extraction of Structural Information from SystemC-based IP for Validation. - David Berner; Hiren D. Patel; Deepak Mathaikutty; Sandeep K. Shukla (MTV, 2005)

System Level Design Methodology for System On Chips using Multi-Threaded Graphs. - Syed Suhaib; Deepak Mathaikutty; Sandeep K. Shukla (SoCC, 2005)

A Functional Programming Framework for Latency Insensitive Protocol Validation. - Syed Suhaib; Deepak Mathaikutty; Sandeep K. Shukla; David Berner; Jean-Pierre Talpin (FMGALS@MEMOCODE, 2005)

XFM: An incremental methodology for developing formal models. - Syed Suhaib; Deepak Mathaikutty; Sandeep K. Shukla; David Berner (ACM Trans. Design Autom. Electr. Syst., 2005)

MCF: A Metamodeling-based Visual Component Composition Framework. - Deepak Mathaikutty; Sandeep K. Shukla (FDL, 2006)

MMV: Metamodeling Based Microprocessor Valiation Environment. - Ajit Dingankar; Deepak Mathaikutty; Sreekumar V. Kodakara; Sandeep K. Shukla; David J. Lilja (HLDVT, 2006)

Polychronous Methodology For System Design: A True Concurrency Approach. - Syed Suhaib; Deepak Mathaikutty; Sandeep K. Shukla; Jean-Pierre Talpin (HLDVT, 2006)

SoC Design Space Exploration through Automated IP Selection from SystemC IP Library. - Deepak Mathaikutty; Sandeep K. Shukla (SoCC, 2006)

A Trace Based Framework for Validation of SoC Designs with GALS Systems. - Syed Suhaib; Deepak Mathaikutty; Sandeep K. Shukla (SoCC, 2006)

Validating Families of Latency Insensitive Protocols. - Syed Suhaib; Deepak Mathaikutty; David Berner; Sandeep K. Shukla (IEEE Trans. Computers, 2006)

CARH: service-oriented architecture for validating system-level designs. - Hiren D. Patel; Deepak Mathaikutty; David Berner; Sandeep K. Shukla (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Design fault directed test generation for microprocessor validation. - Deepak Mathaikutty; Sandeep K. Shukla; Sreekumar V. Kodakara; David J. Lilja; Ajit Dingankar (DATE, 2007)

A Metamodeling based Framework for Architectural Modeling and Simulator Generation. - Deepak Mathaikutty; Ajit Dingankar; Sandeep K. Shukla (FDL, 2007)

Model-driven test generation for system level validation. - Deepak Mathaikutty; Sumit Ahuja; Ajit Dingankar; Sandeep K. Shukla (HLDVT, 2007)

Type Inference for IP Composition. - Deepak Mathaikutty; Sandeep K. Shukla (MEMOCODE, 2007)

Assertion-Based Modal Power Estimation. - Sumit Ahuja; Deepak Mathaikutty; Sandeep K. Shukla; Ajit Dingankar (MTV, 2007)

Model Based Test Generation for Microprocessor Architecture Validation. - Sreekumar V. Kodakara; Deepak Mathaikutty; Ajit Dingankar; Sandeep K. Shukla; David J. Lilja (VLSI Design, 2007)

Dataflow Architectures for GALS. - Syed Suhaib; Deepak Mathaikutty; Sandeep K. Shukla (FMGALS@MEMOCODE, 2007)

EWD: A metamodeling driven customizable multi-MoC system modeling framework. - Deepak Mathaikutty; Hiren D. Patel; Sandeep K. Shukla; Axel Jantsch (ACM Trans. Design Autom. Electr. Syst., 2007)

Metamodeling Driven IP Reuse for System-on-chip Integration and Microprocessor Design. - Deepak Mathaikutty (2007)

Formal Transformation of a KPN Specification to a GALS Implementation. - Syed Suhaib; Bijoy Antony Jose; Sandeep K. Shukla; Deepak Mathaikutty (FDL, 2008)

Applying Verification Collaterals for Accurate Power Estimation. - Sumit Ahuja; Deepak Mathaikutty; Sandeep K. Shukla (MTV, 2008)

SML-Sys: a functional framework with multiple models of computation for modeling heterogeneous system. - Deepak Mathaikutty; Hiren D. Patel; Sandeep K. Shukla; Axel Jantsch (Des. Autom. Embed. Syst., 2008)

Mining metadata for composability of IPs from SystemC IP library. - Deepak Mathaikutty; Sandeep K. Shukla (Des. Autom. Embed. Syst., 2008)

MMV: A Metamodeling Based Microprocessor Validation Environment. - Deepak Mathaikutty; Sreekumar V. Kodakara; Ajit Dingankar; Sandeep K. Shukla; David J. Lilja (IEEE Trans. Very Large Scale Integr. Syst., 2008)

MCF: A Metamodeling-Based Component Composition Framework - Composing SystemC IPs for Executable System Models. - Deepak Mathaikutty; Sandeep K. Shukla (IEEE Trans. Very Large Scale Integr. Syst., 2008)

A Trace-Based Framework for Verifiable GALS Composition of IPs. - Syed Suhaib; Deepak Mathaikutty; Sandeep K. Shukla (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Metamodeling-Driven IP Reuse for SoC Integration and Microprocessor Design. - Deepak Mathaikutty; Sandeep Kumar Shukla (Artech House, 2009)

Power estimation methodology for a high-level synthesis framework. - Sumit Ahuja; Deepak Mathaikutty; Gaurav Singh 006; Joe Stetzer; Sandeep K. Shukla; Ajit Dingankar (ISQED, 2009)

Accurate power estimation of hardware co-processors using system level simulation. - Sumit Ahuja; Deepak Mathaikutty; Avinash Lakshminarayana; Sandeep K. Shukla (SoCC, 2009)

Metamodeling: An Emerging Representation Paradigm for System-Level Design. - Alberto L. Sangiovanni-Vincentelli; Sandeep K. Shukla; Janos Sztipanovits; Guang Yang 004; Deepak Mathaikutty (IEEE Des. Test Comput., 2009)

SCoPE: Statistical Regression Based Power Models for Co-Processors Power Estimation. - Sumit Ahuja; Deepak Mathaikutty; Avinash Lakshminarayana; Sandeep K. Shukla (J. Low Power Electron., 2009)

An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. - Pascal Meinerzhagen; Carlos Tokunaga; Andres Malavasi; Vaibhav A. Vaidya; Ashwin Mendon; Deepak Mathaikutty; Jaydeep Kulkarni; Charles Augustine; Minki Cho; Stephen T. Kim; George E. Matthew; Rinkle Jain; et al. (ISSCC, 2018)

Loihi: A Neuromorphic Manycore Processor with On-Chip Learning. - Mike Davies 002; Narayan Srinivasa; Tsung-Han Lin; Gautham N. Chinya; Yongqiang Cao; Sri Harsha Choday; Georgios D. Dimou; Prasad Joshi; Nabil Imam; Shweta Jain 005; Yuyun Liao; Chit-Kwan Lin; et al. (IEEE Micro, 2018)

An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{ text{MIN}}$ Optimization. - Pascal Andreas Meinerzhagen; Carlos Tokunaga; Andres Malavasi; Vaibhav A. Vaidya; Ashwin Mendon; Deepak Mathaikutty; Jaydeep Kulkarni; Charles Augustine; Minki Cho; Stephen T. Kim; George E. Matthew; Rinkle Jain; et al. (IEEE J. Solid State Circuits, 2019)

Special Session: Approximate TinyML Systems: Full System Approximations for Extreme Energy-Efficiency in Intelligent Edge Devices. - Arnab Raha; Soumendu Kumar Ghosh; Debabrata Mohapatra; Deepak A. Mathaikutty; Raymond Sung; Cormac Brick; Vijay Raghunathan (ICCD, 2021)

Design Considerations for Edge Neural Network Accelerators: An Industry Perspective. - Arnab Raha; Sang Kyun Kim; Deepak Mathaikutty; Guruguhanathan Venkataramanan; Debabrata Mohapatra; Raymond Sung; Cormac Brick; Gautham N. Chinya (VLSID, 2021)

2.4GHz, Double-Buffered, 4kb Standard-Cell-Based Register File with Low-Power Mixed-Frequency Clocking for Machine Learning Accelerators. - Steven Hsu; Amit Agarwal 001; Mark A. Anders 001; Arnab Raha; Raymond Sung; Deepak Mathaikutty; Ram Krishnamurthy 001; James W. Tschanz; Vivek De (VLSI Technology and Circuits, 2022)

Wireless-Assisted Automatic Online Spatial Calibration based on 5G TSN for Sensor Fusion. - Ming Lei; Mahib Rahman; Deepak Mathaikutty; Ignacio Alvarez (ICSPCC, 2023)

VPU-EM: An Event-based Modeling Framework to Evaluate NPU Performance and Power Efficiency at Scale. - Charles Qi; Yi Wang; Hui Wang; Yang Lu; Shiva Shankar Subramanian; Finola Cahill; Conall Tuohy; Victor Li; Xu Qian; Darren Crews; Ling Wang; Shivaji Roy; et al. (CoRR, 2023)

Towards Real-Time LLM Inference on Heterogeneous Edge Platforms. - Rakshith Jayanth; Neelesh Gupta; Souvik Kundu 009; Deepak A. Mathaikutty; Viktor K. Prasanna (HIPCW, 2024)

SwiSS: Switchable Single-Sided Sparsity-based DNN Accelerators. - Shamik Kundu; Soumendu Kumar Ghosh; Arnab Raha; Deepak A. Mathaikutty (ISLPED, 2024)

RASH: Reliable Deep Learning Acceleration using Sparsity-based Hardware. - Shamik Kundu; Arnab Raha; Deepak A. Mathaikutty; Kanad Basu (ISQED, 2024)

HARVEST: Towards Efficient Sparse DNN Accelerators using Programmable Thresholds. - Soumendu Kumar Ghosh; Shamik Kundu; Arnab Raha; Deepak A. Mathaikutty; Vijay Raghunathan (VLSID, 2024)

FlexNN: A Dataflow-aware Flexible Deep Learning Accelerator for Energy-Efficient Edge Devices. - Arnab Raha; Deepak A. Mathaikutty; Soumendu Kumar Ghosh; Shamik Kundu (CoRR, 2024)

LLM-NPU: Towards Efficient Foundation Model Inference on Low-Power Neural Processing Units. - Arnab Raha; Souvik Kundu 009; Sharath Nittur Sridhar; Shamik Kundu; Soumendu Kumar Ghosh; Alessandro Palla; Arghadip Das; Darren Crews; Deepak A. Mathaikutty (COINS, 2025)

OpenAssert: Towards Secure Assertion Generation using Large Language Models. - Anand Menon; Samit Shahnawaz Miftah; Amisha Srivastava; Shamik Kundu; Shovik Kundu; Arnab Raha; Suvadeep Banerjee; Deepak Mathaikutty; Kanad Basu (VTS, 2025)

StruM: Structured Mixed Precision for Efficient Deep Learning Hardware Codesign. - Michael Wu 001; Arnab Raha; Deepak A. Mathaikutty; Martin Langhammer; Nihat Engin Tunali (CoRR, 2025)

GraNNite: Enabling High-Performance Execution of Graph Neural Networks on Resource-Constrained Neural Processing Units. - Arghadip Das; Shamik Kundu; Arnab Raha; Soumendu Kumar Ghosh; Deepak Mathaikutty; Vijay Raghunathan (CoRR, 2025)

XAMBA: Enabling Efficient State Space Models on Resource-Constrained Neural Processing Units. - Arghadip Das; Arnab Raha; Shamik Kundu; Soumendu Kumar Ghosh; Deepak Mathaikutty; Vijay Raghunathan (CoRR, 2025)

Enhancing Large Language Models for Hardware Verification: A Novel SystemVerilog Assertion Dataset. - Anand Menon; Samit S. Miftah; Shamik Kundu; Souvik Kundu 009; Amisha Srivastava; Arnab Raha; Gabriel Theodor Sonnenschein; Suvadeep Banerjee; Deepak Mathaikutty; Kanad Basu (CoRR, 2025)

Accelerating LLM Inference with Flexible N:M Sparsity via A Fully Digital Compute-in-Memory Accelerator. - Akshat Ramachandran; Souvik Kundu 009; Arnab Raha; Shamik Kundu; Deepak A. Mathaikutty; Tushar Krishna (CoRR, 2025)