Design of 56 Gb/s PAM4 wire-line receiver with ring VCO based CDR in a 65 nm CMOS technology. - Fangxu Lv; Jianye Wang; Dengjie Wang; Yongcong Liu; Ziqiang Wang (ASICON, 2017)

A 47mW Two-Dimensional Eye Opening Monitor for Multi-Protocol SerDes. - Wenhuan Luan; Ting Chen; Shuai Yuan 005; Peijie Li; Ziqiang Wang; Xin Lin; Mao Li; Dengjie Wang; Hong Chen 002 (MWSCAS, 2018)

A 4-40 Gb/s PAM-4 transmitter with a hybrid driver in 65 nm CMOS technology. - Dengjie Wang; Hong Chen 002; Wenhuan Luan; Xin Lin; Fangxu Lv; Ziqiang Wang; Hanjun Jiang; Chun Zhang; Zhihua Wang 001 (MWSCAS, 2019)

A 40 Gbps PAM-4 Receiver with 12-Tap Direct Decision Feedback Equalizer Employing 1.5-stage Slicers in 65-nm CMOS. - Zeliang Zhao; Xin Wu; Dengjie Wang; Ziqiang Wang; Chun Zhang; Xiangyu Li; Zhihua Wang 001 (ICTA, 2021)

An 11.05 mW/Gbps Quad-Channel 1.25-10.3125 Gbps Serial Transceiver With a 2-Tap Adaptive DFE and a 3-Tap Transmit FFE in 40 nm CMOS. - Hong Chen 002; Dengjie Wang; Ziqiang Wang; Shuai Yuan 005; Chun Zhang; Zhihua Wang 001 (IEEE Access, 2021)

A 56-Gbps PAM-4 Wireline Receiver With 4-Tap Direct DFE Employing Dynamic CML Comparators in 65 nm CMOS. - Dengjie Wang; Ziqiang Wang; Hao Xu; Jiawei Wang 004; Zeliang Zhao; Chun Zhang; Zhihua Wang 001; Hong Chen 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)