An 8-Bit 0.333-2 GS/s Configurable Time-Interleaved SAR ADC in 65-nm CMOS. - Dengquan Li; Liang Zhang; Zhangming Zhu; Yintang Yang (J. Circuits Syst. Comput., 2015)

A 10-GS/s 6-Bit Track-and-Hold Amplifier for Time-Interleaved SAR ADCs in 65-nm CMOS. - Liang Zhang; Dengquan Li; Zhangming Zhu; Yintang Yang (J. Circuits Syst. Comput., 2016)

A background fast convergence algorithm for timing skew in time-interleaved ADCs. - Dengquan Li; Zhangming Zhu; Liang Zhang; Yintang Yang (Microelectron. J., 2016)

A Background Timing Skew Calibration Technique in Time-Interleaved ADCs With Second Order Compensation. - Dengquan Li; Ruixue Ding; Zhangming Zhu; Yintang Yang (APCCAS, 2018)

A 10-bit 100-MS/s 5.23-mW SAR ADC in 0.18-μm CMOS. - Rui Ma 007; Lisha Wang; Dengquan Li; Ruixue Ding; Zhangming Zhu (Microelectron. J., 2018)

A 1.4-mW 10-Bit 150-MS/s SAR ADC With Nonbinary Split Capacitive DAC in 65-nm CMOS. - Dengquan Li; Zhangming Zhu; Ruixue Ding; Yintang Yang (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 7b 2.6mW 900MS/s Nonbinary 2-then-3b/cycle SAR ADC with Background Offset Calibration. - Dengquan Li; Jiaxin Liu; Haoyu Zhuang; Zhangming Zhu; Yintang Yang; Nan Sun 001 (CICC, 2019)

A 10-Bit 600-MS/s Time-Interleaved SAR ADC With Interpolation-Based Timing Skew Calibration. - Dengquan Li; Zhangming Zhu; Ruixue Ding; Maliang Liu; Yintang Yang; Nan Sun 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 7-bit 900-MS/s 2-Then-3-bit/cycle SAR ADC With Background Offset Calibration. - Dengquan Li; Zhangming Zhu; Jiaxin Liu; Haoyu Zhuang; Yintang Yang; Nan Sun 001 (IEEE J. Solid State Circuits, 2020)

An 8-Bit 2.1-mW 350-MS/s SAR ADC With 1.5 b/cycle Redundancy in 65-nm CMOS. - Dengquan Li; Maliang Liu; Lei Zhao; Henghui Mao; Ruixue Ding; Zhangming Zhu (IEEE Trans. Circuits Syst., 2020)

A Dual-Supply Two-Stage CMOS Op-amp for High-Speed Pipeline ADCs Application. - Maliang Liu; Dengquan Li; Zhangming Zhu (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

27.1 A 250kHz-BW 93dB-SNDR 4th-Order Noise-Shaping SAR Using Capacitor Stacking and Dynamic Buffering. - Jiaxin Liu; Dengquan Li; Yi Zhong; Xiyuan Tang; Nan Sun 001 (ISSCC, 2021)

A 32-GS/s Front-End Sampling Circuit Achieving >39 dB SNDR for Time-Interleaved ADCs in 65-nm CMOS. - Lei Zhao; Dengquan Li; Henghui Mao; Ruixue Ding; Zhangming Zhu (J. Circuits Syst. Comput., 2021)

A statistical offset calibration technique for 1.5-bit/cycle SAR ADCs. - Dengquan Li; Maliang Liu; Shubin Liu; Yuhua Liang; Ruixue Ding (Microelectron. J., 2021)

A TD-ADC for IR-UWB Radars With Equivalent Sampling Technology and 8-GS/s Effective Sampling Rate. - Zhangming Zhu; Yu Zhu; Dengquan Li; Maliang Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A Wideband High-linearity Input Buffer Based on Cascade Complementary Source Follower. - Tian Feng; Dengquan Li; Jiale Ding; Shubin Liu; Yi Shen 007; Zhangming Zhu (ICTA, 2022)

Analysis and Design of a High-Bandwidth Front-End Sampler for Time-Interleaved ADCs. - Jiale Ding; Yukai Huang; Dengquan Li; Shubin Liu; Yi Shen 007; Zhangming Zhu (Circuits Syst. Signal Process., 2022)

A loop-unrolled assisted 9b 700 MS/s nonbinary 2b/cycle SAR ADC with time-based offset calibration. - Yukai Huang; Jiale Ding; Dengquan Li; Xin Zhao 035; Shubin Liu; Yi Shen 007; Zhangming Zhu (Microelectron. J., 2022)

Radio frequency analog-to-digital converters: Systems and circuits review. - Dengquan Li; Xin Zhao 035; Shubin Liu; Maliang Liu; Ruixue Ding; Yuhua Liang; Zhangming Zhu (Microelectron. J., 2022)

A configurable nonbinary 7/8-bit 800-400 MS/s SAR ADC in 65 nm CMOS. - Henghui Mao; Dengquan Li; Shubin Liu (Microelectron. J., 2022)

A 10-Bit 2.5-GS/s Two-Step ADC With Selective Time-Domain Quantization in 28-nm CMOS. - Maliang Liu; Chenxi Zhang; Shubin Liu; Dengquan Li (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Power-Efficient TVC-Based Fast Auto-Frequency Calibration for PLLs. - Depeng Sun; Ruixue Ding; Feng Bu; Hongzhi Liang; Dengquan Li; Yuhua Liang; Shubin Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Fast Convergence Second-Order Compensation for Timing Skew in Time-Interleaved ADCs. - Dengquan Li; Lei Zhao; Longsheng Wang; Yi Shen 007; Zhangming Zhu (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A 12b 1.5GS/s Single-Channel Pipelined SAR ADC with a Pipelined Residue Amplification Stage. - Yi Shen 007; Shubin Liu; Yue Cao; Haolin Han; Hongzhi Liang; Zhicheng Dong; Dengquan Li; Ruixue Ding; Zhangming Zhu (CICC, 2023)

A 7-bit 3.8-GS/s 2-Way Time-Interleaved 4-bit/Cycle SAR ADC 16× Time-Domain Interpolation in 28-nm CMOS. - Dengquan Li; Xin Zhao 035; Yi Shen 007; Shubin Liu; Zhangming Zhu (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

An 8-bit 1.5-GS/s Two-Step SAR ADC With Embedded Interstage Gain. - Yi Shen 007; Junyan Hao; Shubin Liu; Zeshuai An; Dengquan Li; Ruixue Ding; Zhangming Zhu (IEEE Trans. Very Large Scale Integr. Syst., 2023)

An 8-bit 1.5-GS/s Voltage-Time Hybrid Two-Step ADC With Cross-Coupled Linearized VTC. - Xin Zhao 035; Dengquan Li; Feida Wang; Yi Shen 007; Shubin Liu; Ruixue Ding; Zhangming Zhu (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Low-Cost Linearity Testing of High-Resolution ADCs Using Segmentation Modeling and Partial Polynomial Fitting. - Dengquan Li; Yexin Zhu; Longsheng Wang; Shubin Liu; Zhangming Zhu (ISCAS, 2024)

A Background Timing Skew Calibration for Time-Interleaved ADCs Based on Frequency Fitness Genetic Algorithm. - Dengquan Li; Longsheng Wang; Yi Shen 007; Shubin Liu; Zhangming Zhu (IEEE Trans. Instrum. Meas., 2024)

LUT-Assisted Particle Swarm Optimization-Based Bit-Weight Calibration for SAR ADCs. - Longsheng Wang; Dengquan Li; Yexin Zhu; Shubin Liu; Ruixue Ding; Zhangming Zhu (IEEE Trans. Instrum. Meas., 2024)

A 4-GS/s 6-Bit Single-Channel TDC-Assisted Hybrid ADC Featuring Power Supply Variation Adaptation for Inter-Stage Gain Error. - Hongzhi Liang; Shubin Liu; Ruixue Ding; Yi Shen 007; Dengquan Li; Zhangming Zhu (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 0.55-mm2 8-bit 32-GS/s TI-SAR ADC with optimized hierarchical sampling architecture. - Jiale Ding; Yukai Huang; Hao Zhang 111; Tian Feng; Feida Wang; Dengquan Li; Zhangming Zhu (Microelectron. J., 2024)

A Wideband Input Buffer Based on Cascade Complementary Source Follower. - Dengquan Li; Tian Feng; Jiale Ding; Yi Shen 007; Shubin Liu; Zhangming Zhu (IEEE Trans. Very Large Scale Integr. Syst., 2024)

FAPSO: Fast Adaptive Particle Swarm Optimization-Based Background Timing Skew Calibration for TI-ADCs. - Longsheng Wang; Dengquan Li; Ruixue Ding; Zhangming Zhu (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 13b 2GS/s Time-Domain Pipelined ADC with Split-CDAC Ping-Pong Residue Transfer and PVT-Robust Self-Tracked Time Amplifier. - Xin Zhao 035; Dengquan Li; Feida Wang; Depan Li; Yi Shen 007; Hongzhi Liang; Zhangming Zhu (CICC, 2025)

24.2 A 14b 1GS/s Single-Channel Pipelined ADC with A Parallel-Operation SAR Sub-Quantizer and A Dynamic-Deadzone Ring Amplifier. - Yue Cao; Yi Shen 007; Shubin Liu; Haolin Han; Hongzhi Liang; Li Dang; Dengquan Li; Ruixue Ding; Zhangming Zhu (ISSCC, 2025)

A 12-bit 1.5-GS/s Single-Channel Pipelined SAR ADC With a Pipelined Residue Amplification Stage. - Yi Shen 007; Shubin Liu; Yue Cao; Haolin Han; Hongzhi Liang; Zhicheng Dong; Dengquan Li; Ruixue Ding; Zhangming Zhu (IEEE J. Solid State Circuits, 2025)