Path runner: an accurate and fast timing analyser. - Denis Deschacht; P. Pinede; Michel Robert; Daniel Auvergne (EURO-DAC, 1990)

Input waveform slope effects in CMOS delays. - Daniel Auvergne; Nadine Azémard; Denis Deschacht; Michel Robert (IEEE J. Solid State Circuits, 1990)

Formal sizing rules of CMOS circuits. - Daniel Auvergne; Nadine Azémard; V. Bonzom; Denis Deschacht; Michel Robert (EURO-DAC, 1991)

TVA: A timing verifier with analytic temporal modelling. - D. Navarro; A. Roy; Michel Robert; Denis Deschacht; Daniel Auvergne (Microprocessing and Microprogramming, 1991)

Synchronous-mode evaluation of delays in CMOS structures. - Denis Deschacht; Michel Robert; Daniel Auvergne (IEEE J. Solid State Circuits, 1991)

Post-layout timing simulation of CMOS circuits. - Denis Deschacht; Michel Robert; Nadine Azémard-Crestani; Daniel Auvergne (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

A new and accurate interconnection delay time evaluation in a general tree-type network. - Denis Deschacht; Christophe Dabrin (ASP-DAC, 1995)

Delay propagation effect in transistor gates. - Denis Deschacht; Christophe Dabrin; Daniel Auvergne (IEEE J. Solid State Circuits, 1996)

Inductance effect for interconnection timing analysis in submicronic circuits. - Grégory Servel; L. B. Kenmei; Fabrice Huret; Erick Paleczny; Patrick Kennis; Denis Deschacht (ICECS, 1999)

On-chip crosstalk evaluation between adjacent interconnections. - Grégory Servel; Denis Deschacht (ICECS, 2000)

Theoretical limits for signal reflections due to inductance for on-chip interconnections. - Denis Deschacht; Grégory Servel; Fabrice Huret; Erick Paleczny; Patrick Kennis (SLIP, 2000)

On-chip interconnections: impact of adjacent lines on timing. - Denis Deschacht; Grégory Servel (ASP-DAC, 2001)

Impact of Low-K on Crosstalk. - Grégory Servel; Denis Deschacht; Françoise Saliou; Jean-Luc Mattei; Fabrice Huret (ISQED, 2002)

Comparison between Different Data Buses Configurations. - Alain Lopez; Denis Deschacht (ISVLSI, 2004)

Performances of Coupled Interconnect Lines: The Impact of Inductance and Routing Orientation. - Denis Deschacht; Alain Lopez (VLSI Design, 2005)

DSM interconnects: importance of inductance effects and corresponding range of length. - Denis Deschacht (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Crosstalk pulsewidth calculation. - Jean-Etienne Lorival; Denis Deschacht (Microelectron. J., 2010)