Design of SOI CMOS operational amplifiers for applications up to 300°C. - Jean-Paul Eggennont; Denis De Ceuster; Denis Flandre; Bernard Gentinne; Paul G. A. Jespers; Jean-Pierre Colinge (IEEE J. Solid State Circuits, 1996)

A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA. - Fernando Silveira; Denis Flandre; Paul G. A. Jespers (IEEE J. Solid State Circuits, 1996)

Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology. - Denis Flandre; Albert Viviani; Jean-Paul Eggermont; Bernard Gentinne; Paul G. A. Jespers (IEEE J. Solid State Circuits, 1997)

Potential and modeling of 1-μm SOI CMOS operational transconductance amplifiers for applications up to 1 GHz. - Jean-Paul Eggermont; Denis Flandre; Jean-Pierre Raskin; Jean-Pierre Colinge (IEEE J. Solid State Circuits, 1998)

Feasibility of the Smart Card in Silicon-On-Insulator (SOI) Technology. - Amaury Nève; Denis Flandre; Jean-Jacques Quisquater (Smartcard, 1999)

Characterization, Simulation and Modeling of PLL under Irradiation Using HDL-A. - I. Martínez; Pierre Delatte; Denis Flandre (BMAS, 2000)

Analysis and Design of a Family of Low-Power Class AB Operational Amplifiers. - Fernando Silveira; Denis Flandre (SBCCI, 2000)

IF MEMS filters for mobile communication. - E. Quevy; Dimitri Galayko; Bernard Legrand; Christian Renaux; Chantal Combi; Denis Flandre; Lionel Buchaillot; Dominique Collard; B. Vigna; Andreas Kaiser (ETFA (2), 2001)

Design of a Branch-Based Carry-Select Adder IP Portable in 0.25 µm Bulk and Silicon-On-Insulator CMOS Technologies. - Amaury Nève; Denis Flandre (VLSI-SOC, 2001)

Analog Circuit Design Using Graded-Channel SOI NMOSFETS. - Marcelo Antonio Pavanello; João Antonio Martino; Denis Flandre (SBCCI, 2001)

Integrated sensor and electronic circuits in fully depleted SOI technology for high-temperature applications. - Laurent Demeus; Vincent Dessard; Albert Viviani; Stephane Adriaensen; Denis Flandre (IEEE Trans. Ind. Electron., 2001)

A 110 nA pacemaker sensing channel in CMOS on silicon-on-insulator. - Fernando Silveira; Denis Flandre (ISCAS (5), 2002)

Design of a branch-based 64-bit carry-select adder in 0.18 µm partially depleted SOI CMOS. - Amaury Nève; Denis Flandre; Helmut Schettler; Thomas Ludwig 004; Gerhard Hellner (ISLPED, 2002)

Operational Amplifier Power Optimization for a Given Total (Slewing plus Linear) Settling Time. - Fernando Silveira; Denis Flandre (SBCCI, 2002)

DNA electrical detection based on inductor resonance frequency in standard CMOS technology. - G. Laurent; Luis Moreno Hagelsieb; Dimitri Lederer; P. E. Lobert; Denis Flandre; J. Remacle; Jean-Pierre Raskin (ESSCIRC, 2003)

MOSFET mismatch in weak/moderate inversion: model needs and implications for analog design. - Laurent Vancaillie; Fernando Silveira; Bernabé Linares-Barranco; Teresa Serrano-Gotarredona; Denis Flandre (ESSCIRC, 2003)

Design of Operational Transconductance Amplifiers with Improved Gain by Using Graded-Channel SOI nMOSFETs. - Salvador Pinillos Gimenez; Marcelo Antonio Pavanello; João Antonio Martino; Stephane Adriaensen; Denis Flandre (SBCCI, 2003)

SOI Technology for Future High-Performance Smart Cards. - Amaury Nève; Denis Flandre; Jean-Jacques Quisquater (IEEE Micro, 2003)

FD MOS SOI circuit to enhance the ratio of illuminated to dark current of a co-integrated a-Si: H photodiode. - Magali Estrada; A. Afzalian; Denis Flandre; Antonio Cerdeira; Héctor Báez-Medina; A. de Lucca (Microelectron. Reliab., 2003)

Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell. - Ilham Hassoune; Amaury Nève; Jean-Didier Legat; Denis Flandre (PATMOS, 2004)

Power-delay product minimization in high-performance 64-bit carry-select adders. - Amaury Nève; Helmut Schettler; Thomas Ludwig 004; Denis Flandre (IEEE Trans. Very Large Scale Integr. Syst., 2004)

A low-power 5 GHz CMOS LC-VCO optimized for high-resistivity SOI substrates. - Pierre Delatte; Gonzalo Picun; Laurent Demeus; Pascal Simon; Denis Flandre (ESSCIRC, 2005)

Ultra-low power flip-flops for MTCMOS circuits. - David Levacq; Vincent Dessard; Denis Flandre (ISCAS (5), 2005)

Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETS. - Salvador Pinillos Gimenez; Marcelo Antonio Pavanello; João Antonio Martino; Denis Flandre (Microelectron. J., 2006)

Low-swing current mode logic (LSCML): A new logic style for secure and robust smart cards against power analysis attacks. - Ilham Hassoune; François Macé; Denis Flandre; Jean-Didier Legat (Microelectron. J., 2006)

Cryogenic operation of graded-channel silicon-on-insulator nMOSFETs for high performance analog applications. - Marcelo Antonio Pavanello; Paula Ghedini Der Agopian; João Antonio Martino; Denis Flandre (Microelectron. J., 2006)

Building Ultra-Low-Power Low-Frequency Digital Circuits with High-Speed Devices. - David Bol; Renaud Ambroise; Denis Flandre; Jean-Didier Legat (ICECS, 2007)

A CMOS High-Q LC Eight-Path Bandpass Filter for Wireless Broadband Applications. - Ahmed El Oualkadi; Jean-Marie Paillot; Said Belkouch; Denis Flandre (ICECS, 2007)

Dynamic differential self-timed logic families for robust and low-power security ICs. - Ilham Hassoune; François Macé; Denis Flandre; Jean-Didier Legat (Integr., 2007)

Low Leakage SOI CMOS Static Memory Cell With Ultra-Low Power Diode. - David Levacq; Vincent Dessard; Denis Flandre (IEEE J. Solid State Circuits, 2007)

Harmonic distortion analysis using an improved charge sheet model for PD SOI MOSFETs. - Joaquín Alvarado; Antonio Cerdeira; Valeria Kilchytska; Denis Flandre (Microelectron. J., 2007)

Efficient Multiple-Valued Signed-Digit Full Adder Based on NDR MOS Structures and its Application to an N-bit Current-Mode Constant-Time Adder. - David Bol; Ilham Hassoune; David Levacq; Denis Flandre; Jean-Didier Legat (J. Multiple Valued Log. Soft Comput., 2007)

Analysis and minimization of practical energy in 45nm subthreshold logic circuits. - David Bol; Renaud Ambroise; Denis Flandre; Jean-Didier Legat (ICCD, 2008)

Impact of Technology Scaling on Digital Subthreshold Circuits. - David Bol; Renaud Ambroise; Denis Flandre; Jean-Didier Legat (ISVLSI, 2008)

Systematic HDL Design of a Delta-Sigma Fractional-N Phase-Locked Loop for Wireless Applications. - Ahmed El Oualkadi; Denis Flandre (ISVLSI, 2008)

Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation. - Rodrigo Trevisoli Doria; Antonio Cerdeira; Jean-Pierre Raskin; Denis Flandre; Marcelo Antonio Pavanello (Microelectron. J., 2008)

Scaling Trends of the AES S-box Low Power Consumption in 130 and 65 nm CMOS Technology Nodes. - Dina Kamel; François-Xavier Standaert; Denis Flandre (ISCAS, 2009)

Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits. - David Bol; Denis Flandre; Jean-Didier Legat (ISLPED, 2009)

Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic. - David Bol; Dina Kamel; Denis Flandre; Jean-Didier Legat (ISLPED, 2009)

Interests and Limitations of Technology Scaling for Subthreshold Logic. - David Bol; Renaud Ambroise; Denis Flandre; Jean-Didier Legat (IEEE Trans. Very Large Scale Integr. Syst., 2009)

The detrimental impact of negative Celsius temperature on ultra-low-voltage CMOS logic. - David Bol; Cédric Hocquet; Denis Flandre; Jean-Didier Legat (ESSCIRC, 2010)

Glitch-induced within-die variations of dynamic energy in voltage-scaled nano-CMOS circuits. - Dina Kamel; Cédric Hocquet; François-Xavier Standaert; Denis Flandre; David Bol (ESSCIRC, 2010)

Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits. - David Bol; Cédric Hocquet; Denis Flandre; Jean-Didier Legat (ISCAS, 2010)

Compact model for single event transients and total dose effects at high temperatures for partially depleted SOI MOSFETs. - Joaquín Alvarado; El Hafed Boufouss; Valeria Kilchytska; Denis Flandre (Microelectron. Reliab., 2010)

ULPFA: A New Efficient Design of a Power-Aware Full Adder. - Ilham Hassoune; Denis Flandre; Ian O'Connor; Jean-Didier Legat (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Nanometer MOSFET Effects on the Minimum-Energy Point of Sub-45nm Subthreshold Logic - Mitigation at Technology and Circuit Levels. - David Bol; Denis Flandre; Jean-Didier Legat (ACM Trans. Design Autom. Electr. Syst., 2010)

Information Theoretic and Security Analysis of a 65-Nanometer DDSLL AES S-Box. - Mathieu Renauld; Dina Kamel; François-Xavier Standaert; Denis Flandre (CHES, 2011)

A Formal Study of Power Variability Issues and Side-Channel Attacks for Nanoscale Devices. - Mathieu Renauld; François-Xavier Standaert; Nicolas Veyrat-Charvillon; Dina Kamel; Denis Flandre (EUROCRYPT, 2011)

Fully-Automated and Portable Design Methodology for Optimal Sizing of Energy-Efficient CMOS Voltage Rectifiers. - Geoffroy Gosset; Denis Flandre (IEEE J. Emerg. Sel. Topics Circuits Syst., 2011)

Harvesting the potential of nano-CMOS for lightweight cryptography: an ultra-low-voltage 65 nm AES coprocessor for passive RFID tags. - Cédric Hocquet; Dina Kamel; Francesco Regazzoni 001; Jean-Didier Legat; Denis Flandre; David Bol; François-Xavier Standaert (J. Cryptogr. Eng., 2011)

Characterization and modelling of single event transients in LDMOS-SOI FETs. - Joaquín Alvarado; Valeria Kilchytska; El Hafed Boufouss; Denis Flandre (Microelectron. Reliab., 2011)

Impact of neutron irradiation on the RF properties of oxidized high-resistivity silicon substrates with and without a trap-rich passivation layer. - C. Roda Neve; Valeria Kilchytska; Joaquín Alvarado; Dimitri Lederer; O. Militaru; Denis Flandre; Jean-Pierre Raskin (Microelectron. Reliab., 2011)

On the UTBB SOI MOSFET performance improvement in quasi-double-gate regime. - Valeria Kilchytska; Denis Flandre; François Andrieu (ESSDERC, 2012)

A 25MHz 7μW/MHz ultra-low-voltage microcontroller SoC in 65nm LP/GP CMOS for low-carbon wireless sensor nodes. - David Bol; Julien De Vos; Cédric Hocquet; François Botman; François Durvaux; Sarah Boyd; Denis Flandre; Jean-Didier Legat (ISSCC, 2012)

Design of an Ultra-Low-Power Multi-Stage AC/DC Voltage Rectifier and Multiplier Using a Fully-Automated and Portable Design Methodology. - Pierre-Antoine Haddad; Geoffroy Gosset; Denis Flandre (J. Low Power Electron., 2012)

Pushing Adaptive Voltage Scaling Fully on Chip. - Julien De Vos; Denis Flandre; David Bol (J. Low Power Electron., 2012)

High-energy neutrons effect on strained and non-strained SOI MuGFETs and planar MOSFETs. - Valeria Kilchytska; Joaquín Alvarado; S. Put; Nadine Collaert; Eddy Simoen; Cor Claeys; Otilia Militaru; Guy Berger; Denis Flandre (Microelectron. Reliab., 2012)

Threshold voltage extraction techniques and temperature effect in context of global variability in UTBB mosfets. - Sergej Makovejev; Babak Kazemi Esfeh; Jean-Pierre Raskin; Denis Flandre; Valeria Kilchytska; François Andrieu (ESSDERC, 2013)

Characterization of ultra-thin silicon strip detectors for hadrontherapy beam monitoring. - Mohamed Bouterfa; Khaled Aouadi; Denis Flandre; Eduardo Cortina Gil (I2MTC, 2013)

Validation of a Novel ultra-thin silicon Strip Detector for Hadron Therapy beam Monitoring. - Mohamed Bouterfa; Denis Flandre (J. Circuits Syst. Comput., 2013)

SleepWalker: A 25-MHz 0.4-V Sub-mm2 7-µW/MHz Microcontroller in 65-nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes. - David Bol; Julien De Vos; Cédric Hocquet; François Botman; François Durvaux; Sarah Boyd; Denis Flandre; Jean-Didier Legat (IEEE J. Solid State Circuits, 2013)

Asymmetric channel doping profile and temperature reduction influence on the performance of current mirrors implemented with FD SOI nMOSFETs. - Michelly de Souza; Bruna Cardoso Paz; Denis Flandre; Marcelo Antonio Pavanello (Microelectron. Reliab., 2013)

Ultra-Low Power High Temperature and Radiation Hard Complementary Metal-Oxide-Semiconductor (CMOS) Silicon-on-Insulator (SOI) Voltage Reference. - El Hafed Boufouss; Laurent A. Francis; Valeria Kilchytska; Pierre Gérard; Pascal Simon; Denis Flandre (Sensors, 2013)

Variability of UTBB MOSFET analog figures of merit in wide frequency range. - Sergej Makovejev; Babak Kazemi Esfeh; Jean-Pierre Raskin; Valeria Kilchytska; Denis Flandre; Vincent Barral; Nicolas Planes; Michel Haond (ESSDERC, 2014)

Understanding the limitations and improving the relevance of SPICE simulations in side-channel security evaluations. - Dina Kamel; Mathieu Renauld; Denis Flandre; François-Xavier Standaert (J. Cryptogr. Eng., 2014)

A Self-Oscillating System to Measure the Conductivity and the Permittivity of Liquids within a Single Triangular Signal. - Sylvain Druart; Denis Flandre; Laurent A. Francis (J. Sensors, 2014)

A Sizing Methodology for On-Chip Switched-Capacitor DC/DC Converters. - Julien De Vos; Denis Flandre; David Bol (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

A 0.48mm2 5μW-10mW indoor/outdoor PV energy-harvesting management unit in a 65nm SoC based on a single bidirectional multi-gain/multi-mode switched-cap converter with supercap storage. - David Bol; El Hafed Boufouss; Denis Flandre; Julien De Vos (ESSCIRC, 2015)

Wide band study of silicon-on-insulator photodiodes on suspended micro-hotplates platforms. - Nicolas André; Guoli Li; Pierre Gérard; Olivier Poncelet; Yun Zeng; Syed Zeeshan Ali; Florin Udrea; Laurent A. Francis; Denis Flandre (ICICDT, 2015)

Analysis and optimization for dynamic read stability in 28nm SRAM bitcells. - Ahmed T. Elthakeb; Thomas Haine; Denis Flandre; Yehea Ismail; Hamdy Abd Elhamid; David Bol (ISCAS, 2015)

A 65 nm CMOS Ultra-Low-Power Impulse Radio-Ultra-Wideband Emitter for Short-Range Indoor Localization. - Mohamad Al Kadi Jazairli; Denis Flandre (J. Low Power Electron., 2015)

A 65 nm 0.5 V DPS CMOS Image Sensor With 17 pJ/Frame.Pixel and 42 dB Dynamic Range for Ultra-Low-Power SoCs. - Numa Couniot; Guerric de Streel; François Botman; Angelo Kuti Lusala; Denis Flandre; David Bol (IEEE J. Solid State Circuits, 2015)

Diamond layout style impact on SOI MOSFET in high temperature environment. - Salvador Pinillos Gimenez; Egon Henrique Salerno Galembeck; Christian Renaux; Denis Flandre (Microelectron. Reliab., 2015)

A Capacitance-to-Frequency Converter With On-Chip Passivated Microelectrodes for Bacteria Detection in Saline Buffers Up to 575 MHz. - Numa Couniot; David Bol; Olivier Poncelet; Laurent A. Francis; Denis Flandre (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

CAMEL: An Ultra-Low-Power VGA CMOS Imager based on a Time-Based DPS Array. - Thomas Haine; François Stas; Guerric de Streel; Cecilia Gimeno; Denis Flandre; David Bol (ICDSC, 2016)

Efficient passive energy harvesters at 950 MHz and 2.45 GHz for 100 μW applications in 65 nm CMOS. - Pierre-Antoine Haddad; Jean-Pierre Raskin; Denis Flandre (ICECS, 2016)

Automated design of a 13.56 MHz corner-robust efficient differential drive rectifier for 10 μA load. - Pierre-Antoine Haddad; Jean-Pierre Raskin; Denis Flandre (ISCAS, 2016)

Towards Securing Low-Power Digital Circuits with Ultra-Low-Voltage Vdd Randomizers. - Dina Kamel; Guerric de Streel; Santos Merino Del Pozo; Kashif Nawaz; François-Xavier Standaert; Denis Flandre; David Bol (SPACE, 2016)

Experimental and simulation analysis of electrical characteristics of common-source current mirrors implemented with asymmetric self-cascode silicon-on-insulator n-channel metal-oxide-semiconductor field-effect transistors. - Rafael Assalti; Lígia Martins d'Oliveira; Marcelo Antonio Pavanello; Denis Flandre; Michelly de Souza (IET Circuits Devices Syst., 2016)

Automated Design of a 13.56 MHz 19µW Passive Rectifier With 72% Efficiency Under 10µA load. - Pierre-Antoine Haddad; Geoffroy Gosset; Jean-Pierre Raskin; Denis Flandre (IEEE J. Solid State Circuits, 2016)

A 16×16 CMOS Capacitive Biosensor Array Towards Detection of Single Bacterial Cell. - Numa Couniot; Laurent A. Francis; Denis Flandre (IEEE Trans. Biomed. Circuits Syst., 2016)

Scaling Trends for Dual-Rail Logic Styles Against Side-Channel Attacks: A Case-Study. - Kashif Nawaz; Dina Kamel; François-Xavier Standaert; Denis Flandre (COSADE, 2017)

An 80-MHz 0.4V ULV SRAM macro in 28nm FDSOI achieving 28-fJ/bit access energy with a ULP bitcell and on-chip adaptive back bias generation. - Thomas Haine; Quoc-Khoi Nguyen; François Stas; Ludovic Moreau; Denis Flandre; David Bol (ESSCIRC, 2017)

Single event effects and total ionising dose in 600V Si-on-SiC LDMOS transistors for rad-hard space applications. - K. Ben Ali; P. M. Gammon; C. W. Chan; F. Li; V. Pathirana; T. Trajkovic; Farzan Gity; Denis Flandre; Valeria Kilchytska (ESSDERC, 2017)

Back-gate bias effect on UTBB-FDSOI non-linearity performance. - B. Kazemi Esfeh; Valeria Kilchytska; Bertrand Parvais; Nicolas Planes; M. Haond; Denis Flandre; Jean-Pierre Raskin (ESSDERC, 2017)

High-efficiency wireless power transfer for mm-size biomedical implants. - Thibault P. Delhaye; Nicolas André; Samuel Gilet; Cecilia Gimeno; Laurent A. Francis; Denis Flandre (IEEE SENSORS, 2017)

Multiple-Wavelength Detection in SOI Lateral PIN Diodes With Backside Reflectors. - Guoli Li; Nicolas André; Pierre Gérard; Syed Zeeshan Ali; Florin Udrea; Laurent A. Francis; Yun Zeng; Denis Flandre (IEEE Trans. Ind. Electron., 2017)

Design of a 2.45-GHz RF Energy Harvester for SWIPT IoT smart sensors. - Pengcheng Xu 002; Denis Flandre; David Bol (A-SSCC, 2018)

Demonstrating an LPPN Processor. - Dina Kamel; Davide Bellizia; François-Xavier Standaert; Denis Flandre; David Bol (ASHES@CCS, 2018)

Gradient importance sampling: An efficient statistical extraction methodology of high-sigma SRAM dynamic characteristics. - Thomas Haine; Johan Segers; Denis Flandre; David Bol (DATE, 2018)

Low-power half-rate dual-loop clock-recovery system in 28-nm FDSOI. - Cecilia Gimeno; Denis Flandre; David Bol (LASCAS, 2018)

A Transient Noise Analysis of Secured Dual-Rail Based Logic Style. - Kashif Nawaz; Itamar Levi; François-Xavier Standaert; Denis Flandre (NGCAS, 2018)

A Battery-Less BLE IoT Motion Detector Supplied by 2.45-GHz Wireless Power Transfer. - Remi Dekimpe; Pengcheng Xu 002; Maxime Schramme; Denis Flandre; David Bol (PATMOS, 2018)

Let's make it Noisy: A Simulation Methodology for adding Intrinsic Physical Noise to Cryptographic Designs. - Kashif Nawaz; Léopold Van Brandt; François-Xavier Standaert; Denis Flandre (PRIME, 2018)

Analysis and Specification of an IR-UWB Transceiver for High-Speed Chip-to-Chip Communication in a Server Chassis. - Cecilia Gimeno; Denis Flandre; David Bol (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A Robust 10-Gb/s Duobinary Transceiver in 0.13-μm SOI CMOS for Short-Haul Optical Networks. - Javier Aguirre; David Bol; Denis Flandre; Carlos Sánchez-Azqueta; Santiago Celma (IEEE Trans. Ind. Electron., 2018)

Multilevel Half-Rate Phase Detector for Clock and Data Recovery Circuits. - Cecilia Gimeno; David Bol; Denis Flandre (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Self-Heating in 28 FDSOI UTBB MOSFETs at Cryogenic Temperatures. - Lucas Nyssens; Arka Halder; Babak Kazemi Esfeh; Nicolas Planes; Michel Haond; Denis Flandre; Jean-Pierre Raskin; Valeriya Kilchytska (ESSDERC, 2019)

Live Demonstration: A Highly Selective Temperature and Humidity Compensated MOX Based Multi-Gas Sensor Module with Bluetooth 5.0 Connectivity. - Sylvain Pétré; Thomas Walewyns; Roussin Lontio Fomekong; Driss Lahem; Marc Debliquy; Denis Flandre; Laurent A. Francis (IEEE SENSORS, 2019)

A 40-to-80MHz Sub-4μW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI With Dual-Loop Adaptive Back-Bias Generator for 20μs Wake-Up From Deep Fully Retentive Sleep Mode. - David Bol; Maxime Schramme; Ludovic Moreau; Thomas Haine; Pengcheng Xu 002; Charlotte Frenkel; Remi Dekimpe; François Stas; Denis Flandre (ISSCC, 2019)

Methodology for Performance Optimization in Noise- and Distortion-Canceling LNA. - Antonio D. Martínez-Pérez; Cecilia Gimeno; Denis Flandre; Francisco Aznar; Guillermo Royo; Carlos Sánchez-Azqueta (SMACD, 2019)

A battery-less BLE smart sensor for room occupancy tracking supplied by 2.45-GHz wireless power transfer. - Remi Dekimpe; Pengcheng Xu 002; Maxime Schramme; Pierre Gérard; Denis Flandre; David Bol (Integr., 2019)

A security oriented transient-noise simulation methodology: Evaluation of intrinsic physical noise of cryptographic designs. - Kashif Nawaz; Léopold Van Brandt; Itamar Levi; François-Xavier Standaert; Denis Flandre (Integr., 2019)

Analysis, Modeling, and Design of a 2.45-GHz RF Energy Harvester for SWIPT IoT Smart Sensors. - Pengcheng Xu 002; Denis Flandre; David Bol (IEEE J. Solid State Circuits, 2019)

Micrometer-thin SOI Sensors for E-Skin Applications. - Wei Peng; Nicolas André; Xi Zeng; Iman Sabri Alirezaei; Guoli Li; Mohamed Bouterfa; Laurent A. Francis; Denis Flandre (IEEE SENSORS, 2020)

A Practical Approach for the Evaluation of Noise in Oscillator-Based Resistive Sensor Interfaces. - Rafael Puyol; Yannick Molle; Sylvain Pétré; Thomas Walewyns; Laurent A. Francis; Denis Flandre (IEEE SENSORS, 2020)

Anisotropic conductive film & flip-chip bonding for low-cost sensor prototyping on rigid & flex PCB. - Serguei Stoukatch; Nicolas André; Thibault P. Delhaye; François Dupont; Jean-Michel Redouté; Denis Flandre (IEEE SENSORS, 2020)

Learning with Physical Noise or Errors. - Dina Kamel; François-Xavier Standaert; Alexandre Duc; Denis Flandre; Francesco Berti (IEEE Trans. Dependable Secur. Comput., 2020)

Performances Evaluation of On-Chip Large-Size-Tapped Transformer for MEMS Applications. - Fares Tounsi; Denis Flandre; Libor Rufer; Laurent A. Francis (IEEE Trans. Instrum. Meas., 2020)

Improving MOSFET Piezoresistive Strain Gauges Limit of Detection Using Lock-In Principle. - Thibault P. Delhaye; Nicolas Roisin; Nicolas André; Laurent A. Francis; Denis Flandre (IEEE SENSORS, 2021)

SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6-3.6-μW/DMIPS 40-80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode. - David Bol; Maxime Schramme; Ludovic Moreau; Pengcheng Xu 002; Rémi Dekimpe; Roghayeh Saeidi; Thomas Haine; Charlotte Frenkel; Denis Flandre (IEEE J. Solid State Circuits, 2021)

A Self-Gating RF Energy Harvester for Wireless Power Transfer With High-PAPR Incident Waveform. - Pengcheng Xu 002; Denis Flandre; David Bol (IEEE J. Solid State Circuits, 2021)

A Wearable Low-Power Sensing Platform for Environmental and Health Monitoring: The Convergence Project. - Elise Saoutieff; Tiziana Polichetti; Laurent Jouanet; Adrien Faucon; Audrey Vidal; Alexandre Pereira; Sebastien Boisseau; Thomas Ernst 005; Maria Lucia Miglietta; Brigida Alfano; Ettore Massera; Saverio De Vito; et al. (Sensors, 2021)

A 0.9-nA Temperature-Independent 565-ppm/°C Self-Biased Current Reference in 22-nm FDSOI. - Martin Lefebvre 002; Denis Flandre; David Bol (ESSCIRC, 2022)

Spike-Based Sensing and Communication for Highly Energy-Efficient Sensor Edge Nodes. - Florian Roth; Noémie Bidoul; Teodor Rosca; Meik Dörpinghaus; Denis Flandre; Adrian M. Ionescu; Gerhard P. Fettweis (JC&S, 2022)

Design-Window Methodology for Inductorless Noise-Cancelling CMOS LNAs. - Antonio D. Martínez-Pérez; Francisco Aznar; Denis Flandre; Santiago Celma (IEEE Access, 2022)

Variation Range of Different Inductor Topologies with Shields for RF and Inductive Sensing Applications. - Fares Tounsi; Mohamed Hadj Said; Margo Hauwaert; Sinda Kaziz; Laurent A. Francis; Jean-Pierre Raskin; Denis Flandre (Sensors, 2022)

Accurate and Insightful Closed-Form Prediction of Subthreshold SRAM Hold Failure Rate. - Léopold Van Brandt; Roghayeh Saeidi; David Bol; Denis Flandre (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Comprehensive Analytical Comparison of Ring Oscillators in FDSOI Technology: Current Starving Versus Back-Bias Control. - Maxime Schramme; Léopold Van Brandt; Denis Flandre; David Bol (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Static and Dynamic Stochastic Analysis of a Temperature-Sensitive VO2 Spiking Neuron. - Noémie Bidoul; Teodor Rosca; Adrian M. Ionescu; Denis Flandre (ESSDERC, 2023)

SPICE Model of SPAD Transient Intrinsic Response Validated using Mixed-Mode TCAD Simulations. - Tom Klauner; Iman Sabri Alirezaei; Nicolas Roisin; Nicolas André; Denis Flandre (ESSDERC, 2023)

Near-IR response of highly-strained Si photodetector linking first principles and TCAD. - Nicolas Roisin; Jean-Pierre Raskin; Denis Flandre (ESSDERC, 2023)

Low-temperature admittance spectroscopy for defect characterization in Cu(In,Ga)(S,Se)2 thin-film solar cells. - Jonathan Parion; Romain Scaffidi; Denis Flandre; Guy Brammertz; Bart Vermang (EUROCON, 2023)

Mutual Inductance Evaluation Between Two Parallel Conductors on a PCB. - Sana Chouaibi; Mohamed Hadj Said; Dorra Nasr; Mossaad Ben Ayed; Denis Flandre; Fares Tounsi (ICECS, 2023)

A 1.1- / 0.9-nA Temperature-Independent 213- / 565-ppm/$^ circ$C Self-Biased CMOS-Only Current Reference in 65-nm Bulk and 22-nm FDSOI. - Martin Lefebvre 002; Denis Flandre; David Bol (CoRR, 2023)

A 1.1-/0.9-nA Temperature-Independent 213-/565-ppm/°C Self-Biased CMOS-Only Current Reference in 65-nm Bulk and 22-nm FDSOI. - Martin Lefebvre 002; Denis Flandre; David Bol (IEEE J. Solid State Circuits, 2023)

Ultra-Scaled Si Nanowire Biosensors for Single DNA Molecule Detection. - Aryan Afzalian; Denis Flandre (Sensors, 2023)

PCB-Based Planar Inductive Loops for Partial Discharges Detection in Power Cables. - Sinda Kaziz; Pietro Romano; Antonino Imburgia; Guido Ala; Halim Sghaier; Denis Flandre; Fares Tounsi (Sensors, 2023)

Analysis and Design of RF Energy-Harvesting Systems With Impedance-Aware Rectifier Sizing. - Pengcheng Xu 002; Denis Flandre; David Bol (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Variability-Aware Noise-Induced Dynamic Instability of Ultra-Low-Voltage SRAM Bitcells. - Léopold Van Brandt; Jean-Charles Delvenne; Denis Flandre (LASCAS, 2024)

Stochastic Nonlinear Dynamical Modelling of SRAM Bitcells in Retention Mode. - Léopold Van Brandt; Denis Flandre; Jean-Charles Delvenne (CoRR, 2024)

A Combined Analytical and Simulation-Based Methodology for Quantifying the Noise-Power-Area Trade-Offs in Biomedical Amplifiers. - Sylvain Favresse; David Bol; Denis Flandre (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Electromechanical Measurements and Modeling of a High-Performance Small-Area Ultra-Thin SOI MEMS Piezoresistive Pressure Sensor. - Xi Zeng; Nicolas André; Eléonore Masarweh; Ottilie Bonfanti; Denis Flandre (IEEE Trans. Instrum. Meas., 2025)

Modeling and Predicting Noise-Induced Failure Rates in Ultra-Low-Voltage SRAM Bitcells Affected by Process Variations. - Léopold Van Brandt; Michele Bonnin; Maurício Banaszeski da Silva; Pascal Bolcato; Gilson I. Wirth; Denis Flandre; Jean-Charles Delvenne (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)