Non-Linear Components for Mixed Circuits Analog Front-End. - Luigi Carro; Adão Antônio de Souza Jr.; Marcelo Negreiros; Gabriel Parmegiani Jahn; Denis Teixeira Franco (DATE, 2000)

FPGA Based Systems with Linear and Non-Linear Signal Processing Capabilities. - Luigi Carro; Denis Teixeira Franco (EUROMICRO, 2000)

FPGA Architecture Comparison for Non-Conventional Signal Processing. - Denis Teixeira Franco; Luigi Carro (IJCNN (2), 2000)

Circuit-Level Considerations for Mixed-Signal Programmable Components. - Luigi Carro; Marcelo Negreiros; Gabriel Parmegiani Jahn; Adão Antônio de Souza Jr.; Denis Teixeira Franco (IEEE Des. Test Comput., 2003)

Yield and reliability issues in nanoelectronic technologies. - Denis Teixeira Franco; Jean-François Naviner; Lirida A. B. Naviner (Ann. des Télécommunications, 2006)

Methods and Metrics for Reliability Assessment. - Lirida Alves de Barros Naviner; Jean-François Naviner; Denis Teixeira Franco; Maí Correia R. de Vasconcelos (Fault-Tolerant Distributed Algorithms on VLSI Chips, 2008)

Reliability analysis of logic circuits based on signal probability. - Denis Teixeira Franco; Maí Correia Vasconcelos; Lirida A. B. Naviner; Jean-François Naviner (ICECS, 2008)

On the output events in concurrent error detection schemes. - Maí Correia R. de Vasconcelos; Denis Teixeira Franco; Lirida A. B. Naviner; Jean-François Naviner (ICECS, 2008)

Signal probability for reliability evaluation of logic circuits. - Denis Teixeira Franco; Maí Correia Vasconcelos; Lirida A. B. Naviner; Jean-François Naviner (Microelectron. Reliab., 2008)

Relevant metrics for evaluation of concurrent error detection schemes. - Maí Correia R. de Vasconcelos; Denis Teixeira Franco; Lirida A. B. Naviner; Jean-François Naviner (Microelectron. Reliab., 2008)

On evaluating the signal reliability of self-checking arithmetic circuits. - Denis Teixeira Franco; Maí Correia Vasconcelos; Lirida A. B. Naviner; Jean-François Naviner (SBCCI, 2010)

A system based on interval fuzzy approach to predict the appearance of pests in agriculture. - Leonardo Martins Rodrigues; Graçaliz Pereira Dimuro; Denis Teixeira Franco; Jose Carlos Fachinello (IFSA/NAFIPS, 2013)

A probabilistic model for stuck-on faults in combinational logic gates. - Rafael B. Schivittz; Denis Teixeira Franco; Cristina Meinhardt; Paulo F. Butzen (LATS, 2016)

Inserting permanent fault input dependence on PTM to improve robustness evaluation. - Rafael B. Schivittz; Rafael Fritz; Denis Teixeira Franco; Lirida A. B. Naviner; Cristina Meinhardt; Paulo F. Butzen (SBCCI, 2016)

Exploring BDDs to reduce test pattern set. - Gabriel S. Porto; Paulo F. Butzen; Denis Teixeira Franco (LATS, 2017)

The Suitability of the SPR-MP Method to Evaluate the Reliability of Logic Circuits. - Matheus F. Pontes; Paulo F. Butzen; Rafael B. Schvittz; Leomar S. da Rosa Jr.; Denis Teixeira Franco (ICECS, 2018)

Probabilistic Method for Reliability Estimation of SP- Networks considering Single Event Transient Faults. - Rafael B. Schvittz; Denis Teixeira Franco; Leomar S. da Rosa Jr.; Paulo F. Butzen (ICECS, 2018)

Reliability evaluation of circuits designed in multi- and single-stage versions. - Rafael B. Schvittz; Matheus F. Pontes; Cristina Meinhardt; Denis Teixeira Franco; Lirida A. B. Naviner; Leomar S. da Rosa; Paulo F. Butzen (LASCAS, 2018)

An Improved Technique for Logic Gate Susceptibility Evaluation of Single Event Transient Faults. - Rafael B. Schvittz; Denis Teixeira Franco; Leomar S. da Rosa; Paulo F. Butzen (VLSI-SoC (Selected Papers), 2019)

A Simplified Layout-Level method for Single Event Transient Faults Susceptibility on Logic Gates. - Rafael B. Schvittz; Denis Teixeira Franco; Leomar Soares; Paulo Francisco Butzen (VLSI-SoC, 2019)