Die stacking using 3D-wafer level packaging copper/polymer through-si via technology and Cu/Sn interconnect bumping. - Yann Civale; Deniz Sabuncuoglu Tezcan; Harold G. G. Philipsen; P. Jaenen; Rahul Agarwal; F. Duval; Philippe Soussan; Youssef Travaly; Eric Beyne (3DIC, 2009)

A novel concept for ultra-low capacitance via-last TSV. - Yann Civale; Marcel Gonzalez; Deniz Sabuncuoglu Tezcan; Youssef Travaly; Philippe Soussan; Eric Beyne (3DIC, 2010)

A 300mm CMOS-Compatible PECVD Silicon Nitride Platform for Integrated Photonics with Low Loss and Low Process Induced Phase Variation. - Sandeep S. Saseendran; Tangla D. Kongnyuy; Bruno Figeys; Federico Buja; Benedetto Troia; Sarp Kerman; Aleksandrs Marinins; Roelof Jansen; Xavier Rottenberg; Deniz Sabuncuoglu Tezcan; Philippe Soussan (OFC, 2019)

Wafer Level Pixelation of Colloidal Quantum Dot Image Sensors. - Yunlong Li; Gauri Karve; Pawel E. Malinowski; Joo Hyoung Kim; Epimitheas Georgitzikis; Vladimir Pejovic; Myung-Jin Lim; Luis Moreno Hagelsieb; Renaud Puybaret; Itai Lieberman; Jiwon Lee; David Cheyns; et al. (VLSI Technology and Circuits, 2022)