A Direct Combination of the Prim and Dijkstra Constructions for Improved Performance-driven Global Routing. - Charles J. Alpert; T. C. Hu; Jen-Hsin Huang; Andrew B. Kahng (ISCAS, 1993)

Quantified Suboptimality of VLSI Layout Heuristics. - Lars W. Hagen; Dennis J.-H. Huang; Andrew B. Kahng (DAC, 1995)

On the Bounded-Skew Clock and Steiner Routing Problems. - Dennis J.-H. Huang; Andrew B. Kahng; Chung-Wen Albert Tsao (DAC, 1995)

When clusters meet partitions: new density-based methods for circuit decomposition. - Dennis J.-H. Huang; Andrew B. Kahng (ED&TC, 1995)

Multi-way System Partitioning into a Single Type or Multiple Types of FPGAs. - Dennis J.-H. Huang; Andrew B. Kahng (FPGA, 1995)

Prim-Dijkstra tradeoffs for improved performance-driven routing tree design. - Charles J. Alpert; T. C. Hu; Dennis J.-H. Huang; Andrew B. Kahng; David R. Karger (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Quadratic Placement Revisited. - Charles J. Alpert; Tony F. Chan; Dennis J.-H. Huang; Igor L. Markov; Kenneth Yan (DAC, 1997)

Faster minimization of linear wirelength for global placement. - Charles J. Alpert; Tony F. Chan; Dennis J.-H. Huang; Andrew B. Kahng; Igor L. Markov; Pep Mulet; Kenneth Yan (ISPD, 1997)

Partitioning-based standard-cell global placement with an exact objective. - Dennis J.-H. Huang; Andrew B. Kahng (ISPD, 1997)

On implementation choices for iterative improvement partitioning algorithms. - Lars W. Hagen; Dennis J.-H. Huang; Andrew B. Kahng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Multilevel circuit partitioning. - Charles J. Alpert; Jen-Hsin Huang; Andrew B. Kahng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Analytical Engines are Unnecessary in Top-down Partitioning-based Placement. - Charles J. Alpert; Andrew E. Caldwell; Tony F. Chan; Dennis J.-H. Huang; Andrew B. Kahng; Igor L. Markov; M. S. Moroz (VLSI Design, 1999)

ePlace: Electrostatics Based Placement Using Nesterov's Method. - Jingwei Lu; Pengwen Chen; Chin-Chih Chang; Lu Sha; Dennis J.-H. Huang; Chin-Chi Teng; Chung-Kuan Cheng (DAC, 2014)

ePlace-MS: Electrostatics-Based Placement for Mixed-Size Circuits. - Jingwei Lu; Hao Zhuang 001; Pengwen Chen; Hongliang Chang; Chin-Chih Chang; Yiu-Chung Wong; Lu Sha; Dennis J.-H. Huang; Yufeng Luo; Chin-Chi Teng; Chung-Kuan Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

PROS: A Plug-in for Routability Optimization applied in the State-of-the-art commercial EDA tool using deep learning. - Jingsong Chen; Jian Kuang 001; Guowei Zhao; Dennis J.-H. Huang; Evangeline F. Y. Young (ICCAD, 2020)

PROS 2.0: A Plug-In for Routability Optimization and Routed Wirelength Estimation Using Deep Learning. - Jingsong Chen; Jian Kuang 001; Guowei Zhao; Dennis J.-H. Huang; Evangeline F. Y. Young (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)