A system level implementation of Rijndael on a memory-slot based FPGA card. - Dennis K. Y. Tong; Pui Sze Lo; Kin-Hong Lee; Philip Heng Wai Leong (FPT, 2002)

Retiming with Interconnect and Gate Delay. - Chris C. N. Chu; Evangeline F. Y. Young; Dennis K. Y. Tong; Sampath Dechu (ICCAD, 2003)

Performance-driven register insertion in placement. - Dennis K. Y. Tong; Evangeline F. Y. Young (ISPD, 2004)

Wire Retiming Problem With Net Topology Optimization. - Dennis K. Y. Tong; Evangeline F. Y. Young; Chris C. N. Chu; Sampath Dechu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)